F-Tile debug toolkit not loading properly

[Vasileios_Anastasiou]

Hi.

I'm using an SDI example design with serial loopback generated with Quartus Prime Pro 24.3 for Agilex7 (AGFB027R24C2E2V device) FPGA. I'm trying to load the F-tile transceiver toolkit for the RX Channel. I invoke from my Quartus project the System Debugging Tools. After adding the FGT instance to a new collection and press the "Open Toolkit" button, I'm getting the following error on the System Console:

Feb 11, 2025 3:21:54 PM Intel F-Tile Transceiver Toolkit: ftile_transceiver_toolkit1739287313013
SEVERE: An error occurred while running script "ftile_callback_pkg::init_callback
": Intel F-Tile Transceiver Toolkit: ftile_transceiver_toolkit1739287313013: can't create directory "C:/Users/VASILE~1ANA": permission denied
while executing
"file mkdir $temp_no_slash"
(procedure "temp_dir" line 6)
invoked from within
"temp_dir"
(procedure "exec_pysv_server" line 6)
invoked from within
"exec_pysv_server"
(procedure "pysv_driver::start" line 23)
invoked from within
"pysv_driver::start"
(procedure "ftile_callback_pkg::init_callback" line 20)
invoked from within
"ftile_callback_pkg::init_callback"

It seems that it's not liking the path that it's trying to create that temp directory. However these scripts for the toolbox are invoked from the Quartus Prime Pro installation directory and cannot be changed. Is there a workaround on this issue?

[Wincent_Altera]

Hi,

Based on provided information, the issue was failing at the basic step and the system-console is not able to create tmp directory in the User directory.

Could you try to test with the different User or create a directory manually in the folder where see the error?

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Altera

[Vasileios_Anastasiou]

Hi,

I haven't tried your solution yet on my system. I will do so today and let you know.

Regards,

Vasileios Anastasiou

[Vasileios_Anastasiou]

Hi again,

I've tried creating a directory in the user location where the TCL script (ftile_pysv_driver_pkg.tcl) is trying to create it and it's still failing with permission denied. My question is why doesn't it try to create the temp directory on the project directory where the system console is being invoked from? And also if that's the case is there any way to point the TCL script to the desired directory? 

Just to elaborate the failing process of the script is below:

proc temp_dir { } {
set fd [file tempfile temp]
close $fd
file delete $temp
set temp_no_slash [regsub -all {\.} $temp ""]
file mkdir $temp_no_slash
#dprint 1 "Temporary directory @ $temp"
return $temp_no_slash
}

After running the set temp_no_slash [regsub -all {\.} $temp ""] on the system console I'm getting the following result: 

C:/Users/VASILE~1ANA/AppData/Local/Temp/TCL63582TMP

And the the file mkdir command is failing. 

[Wincent_Altera]

Hi ,

Normally within C drive it will be fine.
We have latest version of Quartus which is v24.3.1 , is it possible for you to try on that version ?

After adding the FGT instance to a new collection and press the "Open Toolkit" button, I'm getting the following error on the System Console:
>> Just try to understand from you, if purely from the design example without adding FGT, the toolkit work fine , am I correct on this ?

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Hoping to hear back from you so that we can proceed for next step.

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

Just check again, if you have any update on my previous clarification.

Regards,

Wei Chuan

[Vasileios_Anastasiou]

Hi again.

I've got an update for you. I tried to use Quartus v24.3.1 but still getting the same error as before about not being able to create a directory in the user location. 

"Just try to understand from you, if purely from the design example without adding FGT, the toolkit work fine , am I correct on this ?"

I'm not adding FGT. The F-Tile transceiver exists in the original example design. All I'm trying to do is add some debug to it, to be able to view the eye of the signal on the Rx side. To do that I'm adding the debug option as described in your guide: 

7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug

Attached you'll find a snapshot of what I'm trying to do and I'm getting the error about the user directory failing to create.

[Wincent_Altera]

Hi Vasileios,

First things. to clarified, If I check back your initial message and your device OPN.

• You are using "AGF" F-series device, FYI our F-tile SDI II design example is only supported "AGI series" of device
• https://www.intel.com/content/www/us/en/docs/programmable/710496/24-2-19-5-0/hardware-and-software-requirements.htmlif you need it to be fully supported, some customization of custom code might be needed
• 

Second and the most important,

• Our Agilex device for SDI II IP does not supported either Transceiver Toolkit or Debug Toolkit.
• the IP GUI does not have option to enable "TTK" or "DTK" as well. 
• 
• But for PCIE design example gen5 https://community.intel.com/t5/FPGA-Intellectual-Property/How-to-run-PCIe-Gen-5-Design-Example-using-Altera-FPGA-device/td-p/1640988 the option is there for DTK in PCIe design, but not for SDI II either in F-series or I-series.
• But for Arria 10 , we have an design example to enable it Intel® Arria® 10 FPGA – Triple-Rate SDI with Transceiver Toolkit Reference Design perhaps you can refer that.

is it compulsory for you to run the debug toolkit ? Any reason needed for that ?
Perhaps you could consider something alternative like SignalTap could be a helpful tools for debugging

Regards,
Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Altera

[Vasileios_Anastasiou]

Good morning.

I'm using "AGF"  F-series device because this is the part that is on the development board the SDI example design is running.

As for you second bullet point is that a prerequisite for the transceiver debug toolkit to run? Because I'm only enabling the debugging capabilities in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, which is part of the SDI example design and is connected to the SDI II IP.

The reason we want to run the transceiver debug toolkit is to be able to view the eye of the signal received in Rx. At the moment we don't have an analyzer that supports 12G multi-rate SDI signal and we were hoping that by checking the eye of the signal, when 12G rate is selected, we would be confident that the design is working within the requirements specified by the protocol.

Obviously we've checked it's working with SignalTap and that the Rx is locking at the 12G multirate mode. Just an extra visualization of the signal. If this is not supported then you can close this ticket. 

Thank you for all the help.

Regards,

Vasileios Anastasiou.

[Wincent_Altera]

Hi Vasileios,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have new question, please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of ddesire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.

Regards,
Wincent_Altera