Dual DDR connection to Agilex 5

[JosefH]

Hello

we try to find answer, and confirm by compilation, if we can connect two 1x16 LPDDR4 memories to one HSIO bank 3A in Agilex 5 SOC (each DDR connected to different sub-bank). One DDR is reserved for HPS and second for FPGA fabric access. We compile it for A5ED065BB32AE6SR0 which is used in Arrow DevKit, even this configuration is not possible to test with the real HW now. We cannot find any setting for successful compilation. We try to configure two EMIFs, one for HPS, one for fabric. We want to connect one dual channel LPDDR4 (dual die package e.g W66CP2NQQAFJ) to SOC in order to save space on PCB.

JosefH

[AdzimZM_Intel]

Hi JosefH,

I think you may need to follow the restriction on I/O bank usage for Agilex 5 since there are multiple configuration that allow and not allow to share the I/O Bank with HPS-EMIF IP.

Please the I/O bank usage in this link: https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/emif-ip-for-hard-processor-subsystem-hps.html#dropdown-1-2-4

Regards,

Adzim

[JosefH]

Hi Adzim

We think we meet the HPS-EMIF restrictions described in the EMIF user guide. There are only not so clear the following restrictions:

• Reference clock sharing is not allowed between HPS-EMIF IP and other IPs.
  • There are only the next parameters configurable from the platform designer for HPS-EMIF, DDRAM width, and DDRAM type (DDR4/LPDDR4/..). We see in the top file of the project that two different REF_CLK signals are used, and these signals are reserved only for specific EMIFs, not for other IPs.
• For multi-channel EMIFs or when multiple EMIFs are used inside HPS-EMIF IP, they must have identical IP parameters.
  • Again, only the next parameters are configurable by the platform designer for HPS-EMIF, DDRAM width, and DDRAM type (DDR4/LPDDR4/..). Therefore, it is hard to completely confirm that both EMIF IPs (Fabric EMIF, HPS EMIF) use identical parameters.
  • It is unclear to us what multiple EMIFs used inside HPS-EMIF mean.

Again, I repeat our question: Is it possible to use HPS-EMIF and Fabric-EMIF (1x16 LPDDR4) connected to one HSIO bank 3A? If yes, how to configure it? There are no other signals connected to such an HSIO bank

Thanks for any comment, Josef

[sstrell]

For the second bullet you mention, that applies to if you implement multiple HPS EMIFs.  All of them (that you can fit; only 2 I/O banks available to the HPS) must have the same parameters.  This is not required between an HPS EMIF and a separate fabric EMIF.

The answer to your question, though, is no.  Bank 3A is specifically reserved for an HPS EMIF.

[JosefH]

Thanks for your reply.

Can you describe where this restriction is mentioned in the documentation? We found several notices regarding the EMIF and HPS-EMIF restriction, but not essentially this impossibility.

We will try to test two alternative solutions for sharing LPDDR4 using HSP and FPGA fabric in parallel.

The first idea is to use HPS-EMIF with dual x16 LPDDR4 in combination with an F2SDRAM bridge. We want to check parallel access F2SDRAM to one channel x16 LPDDR4 and HPS to second x16 LPDDR4.

The second idea is to use 1x32 LPDDR4 and an interleaved access HPS / F2SDRAM bridge to two memory spaces. We want to check for possible collisions in parallel memory access and their influence on the required memory response speed. 

Does anybody have an experience with such DDR sharing?

Thanks for your response. Josef

[sstrell]

It says it right at the top of the web page that was linked to: 

The following restrictions apply to the I/O bank usage:

• Only the two IO96 banks adjacent to the HPS MPFE can be used for HPS-EMIF. (Banks 3A and 3B.)
• If only one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE. (Bank 3A.)