Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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F-tile JESD IP RX data timing diagram

Hruthik_9999
初學者
488 檢視

Hi,

 

I'm Configuring Intel JESD IP with LMFS=2881,with this configuration i'm getting 8 converters data and i'm not able to decode data belongs to which Converter.I have been checking for timing diagram for jesd IP RX signals but i'm not able to find it.Could you please provide timing diagram where it will show sof(start of frame) and rx_link_data[63:0]

 

Thanks

Hruthik

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Harshx
員工
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We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

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Harshx
員工
280 檢視

Hi,

You can get timing details from Compilation Report -> Timing Analyzer.

Regards,

Harsh M


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