F-tile Reference and System PLL Clocks: mising port documentation

[SDe_J]

Hello Intel forums,

I'm exploring the settings of the "F-Tile Reference and System PLL Clocks Intel FPGA" IP.

There is a setting "Refclk #X is active at and after device configuration" which is enabled by default. If I disable this setting, some new ports are added to the IP instance:

• avmm_clk                              : in std_logic := 'X'; -- clk
• avmm_reset                          : in std_logic := 'X'; -- reset
• refclock_ready                      : in std_logic_vector(2 downto 0) := (others => 'X'); -- refclock_ready
• refclock_status                       : out std_logic; -- refclock_status
• en_refclk_fgt_0                       : in std_logic := 'X'; -- en_refclk_fgt_0
• disable_refclk_monitor_0    : in std_logic := 'X'; -- disable_refclk_monitor_0
• refclk_fgt_enabled_0            : out std_logic -- refclk_fgt_enabled_0

I have looked at the documentation on implementing the IP (Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP) but these ports are not documented. Can you explain what each does?

Why does "refclk_ready" have three bits? Does each bit correspond to a system clock?

I'm not using the system clock in my implementation, does that mean I only need to set "en_refclk_fgt_0" to '1' when that clock is ready?

Do I always need to provide an avmm_clk and avmm_reset?

Thank you for your assistance.

[AqidAyman_Intel]

Hi,

The link you provided is not the latest version of the document.

You may refer to the link below for the updated version. There are guidelines documented for this specific setting.

https://www.intel.com/content/www/us/en/docs/programmable/683872/25-1-1/guidelines-for-refclk-i-is-active-at.html

Regards,

Aqid

[AqidAyman_Intel]

Hi,

Do you still need assistance with this question from my last answer?

Regards,

Aqid

[SDe_J]

Thank you for your assistance, this updated documentation answers most of my questions.

I have a followup question about the 'out_coreclk_i' ports. The documentation states that this can be used to drive user logic, but not IOPLLs. I am trying to use this for that purpose, but I'm getting this error which I don't understand:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PLDADAPT_RX(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic HSSI_PLDADAPT_RX in region (11, 71) to (11, 71), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_PLDADAPT_RX name(s): agilex_devkit_top_auto_tiles|z1577b_x1_y2_n0|hdpldadapt_rx_chnl_23
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Info(175013): The HSSI_PLDADAPT_RX is constrained to the region (11, 71) to (11, 71) due to related logic
Info(175015): The HSSI_Z1577B agilex_devkit_top_auto_tiles|z1577b_x1_y2_n0|z1577b is constrained to the region (1, 2) to (1, 2) due to: User Location Constraints (Z1577B_X1_Y2_N0)
Info(14709): The constrained HSSI_Z1577B drives this HSSI_PLDADAPT_RX
Error(175006): There is no routing connectivity between the HSSI_PLDADAPT_RX and destination core logic
Info(175027): Destination: core logic CORE_LOGIC_OF_agilex_devkit_top_auto_tiles|z1577b_x1_y2_n0|x0_x0_u25_2_hdpldadapt_pld_pma_internal_clk1_hioint
Error(175022): The HSSI_PLDADAPT_RX could not be placed in any location to satisfy its connectivity requirements
Info(175021): The destination core logic was placed in location CORE_LOGIC
Info(175029): 1 location affected
Info(175029): HSSIPLDADAPTRX_1F5 

I have some altera_fifo instances in my user logic, are they not able to be driven by 'out_coreclk_i'?

The documentation states: "Note: This signal cannot directly feed the reference clock of the IOPLL Intel FPGA IP."

Is there a way to indirectly feed the reference clock of the IOPLL?

Thank you for your assistance.

Cheers,
Sam

[Farabi · Accepted solution]

Hello,

Q1- Can out_coreclk_i used to drive IOPLL?

<ANS> No. out_coreclk_i is not routed through dedicated clock paths required by IOPLL.

Q2- Is there workaround to indirectly use out_coreclk_i for IOPLL reference?

<ANS> a. Use Clock Control IP.

b. Use dedicated clk routing.

Q3- Fitter error and HSSI_PLDADAPT_RX

<ANS> error is due to placement constraints and routing limitation between HSSI components and core logic. In your case, HSSI_PLDADAPT_RX is constrained to a specific region, but the core logic needs to connect to is placed elsewhere, and there is no valid routing path. Please review your location constraints. Avoid using out_coreclk_i for clocking components that require dedicated routing.

Q4- Can altera_fifo be driven by out_coreclk_i ?

<ANS> yes, they are not dependent on IOPLL reference. FIFO IP is designed to work with fabric routing.

regards,

Farabi

[SDe_J]

Hi Farabi,

Thank you for your assistance, these answers are helpful. I will close this thread now.

Cheers,
Sam