I am attempting to use the F2SDRAM bridge on my board to transfer data from my FPGA to the DDR3 of my HPS. However, when looking at the signal tap for my system, the FPGA writes 17 times, then the F2SDRAM waitrequest goes high an stays high. Also, the data doesnt actually get written to the DDR3 section of memory indicated for the 17 writes that appear to go through. I am using the Avalon-MM Pipeline Bridge module combined with the F2SDRAM. I also updated the preloader and uboot, but still not effect. Thanks! Also if anyone has an example project that does something like this I would appreciate it.
EDIT: I changed the BSP-Editor Setting Labeled Advnaced=>spl.warm_reset_handshake=>SDRAM to on and now the first write shows up in DDR3, but none of the others, and the waitrequest from the bridge still goes high after 17 writes.