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alperenpalp
Novice
431 Views

FIR II core IP outputs incorrect data.

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Hello,

It's my first time using intel's FIR filter IP and I'm having difficulties getting it working.

I basically want to low-pass filter the data coming from the ADC (LTC2387) using FIR II IP. The filter is fractional rate filter.

Here are some of the filter specs:

Input sampling rate: 15 MSPS

Filter clock : 60 MHz

Coeffs: 51 taps, 16-bit signed binary

Input 16-bit singed binary

Output: 36-bit signed binary.

The data coming from the ADC is in 2's complement, and therefore firstly I convert it to signed binary(bit magnitude) and feed the converted data to the filter's input.

To make sure that everything's working I make the input to the filter constant and observe the output, expecting that the output stays constant as well, but it doesn't.

The input is constant -256 (FF00h in 2s complement 8100h in signed magnitude) and the output looks quite random as you can see in the attachment.

I also attached the archieve file which include the filter I am using. The filter is in pre_process_20MSPS.vhd file along with the conversion from 2's comlement to singed magnitude process.

What am I doing wrong?

 

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Accepted Solutions
CheePin_C_Intel
Employee
151 Views

Hi,

Would you mind to help opening a new thread on this. Thank you very much.

View solution in original post

22 Replies
alperenpalp
Novice
378 Views

The output rate is 20MSPS. I forgot to add this.

I hope someone can help me with this.

Thanks.

CheePin_C_Intel
Employee
367 Views

Hi,


Sorry for the delay. As I understand it, you observe some issue with the FIR II IP. If I understand it correctly, you are observing it in simulation. To ensure we are on the same page, would you mind to share with me a simple Modelsim simulation example together with steps which could replicate your observation? Some screenshots to further elaborate on the issue would be very helpful. Thank you very much.


alperenpalp
Novice
361 Views

Hello,

Thank you for your answer,

I am observing the output of the FIR filter (FIR filter output (36 bit data)) in signal tap, so it's not modelsim simulation, it's real hardware implementation. Signal Tap file is also included in the .qar file that I shared.

I understand that the file I shared is kind of complicated it's a portion of our design we working on I am sorry for its messiness. I kindly ask you to inspect pre_process IP. I t includes the FIR filter and data conversion(2's complement to bit magnitude conversion for the input).

This is my understanding on how the IP works:

I only need a signle channel therefore the error signals kind of irrelevant (no SOP or EOP), therefore I ignored them left them 'open' in the VHDL file. Sink side has an error input I don't know what to do with that. The input is 16-bit signed binary,  I assume this bit magnitude form where the first bit is the sign and the rest is the number. The input 15MSPS, the output 20MSPS, the clock to the filter is 60MHz. What I do is I fixed the input signal at 0x8100 and assert sink valid at every 4th(60MHz/15MSPS = 4) cycle of the clock and expect the source valid to be asserted at every third cycle of the clock which is what we see in the waveform that I attached, but the output looks completely random.

What am I doing wrong? 

CheePin_C_Intel
Employee
354 Views

Hi,


Thanks for your update. As I understand it, you are observing this in signaltap. To help isolating any functional issue, it is recommended for you to create simple test design and run through Modelsim simulation to check on the behavior. Generally the Modelsim simulation behavior is similar to the hardware behavior for this IP. This would help to isolate any functional issue prior to hardware debugging. Please feel free to keep me posted on the simulation result.


Regarding the ast_sink_error, this is to indicate AVST violation to the IP. In normal cases, you can drive the ports with 2'b00.


Regarding the SOP/EOP, yes, you are right. For single channel, you do not need these ports. By default, when you select single channel, there will be no SOP/EOP ports.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin



alperenpalp
Novice
345 Views

Thank you for your kind response,

OK I am going to start with a testbench, but I want to quickly confirm one thing. Is Singed binary same as bit magnitude where the first represents the sign and the rest is the number. I am talking about Input and output type in Input/Output Options settings.

I wrote a simple test bench and tested the FIR filter (attached). I share the results with a screenshot. As you see the input is fixed at some value, the clock to the filter is 60 MHz and every fourth cycle of the I asserted the sink_valid signal for one cycle and I see don't see any output. No action from the filter.

See the attached files for the test bench it's named FIR_tb.vhd. I know there is another tb file generated by quartus, but failed to get it working. I simply instantianted pre_process_FIR_20MSPS_0002 IP and tried to get it working.

FIR_tb.vhd

Thanks in advance.

CheePin_C_Intel
Employee
337 Views

Hi,


Thanks for your update. yes, the signed binary, the MSBits = sign bit. Please allow me some time to look into your shared test bench. I will be out of office and back on next Tuesday due to local Public holiday. I will keep you posted on the progress by mid of next week or as soon as there is any valid finding. Please ping me if you do not hear back from me.


Thank you.


CheePin_C_Intel
Employee
313 Views

Hi,

Sorry for the delay. As I understand it from your screenshot, seems like the source data = undefined in your simulation. Sorry as I am not very familiar with VHDL and could not really further edit your test bench for testing.

To facilitate your debugging, I have generated a simple simulation example from the IP with 16 bits coeff and 16 bits input signed data using A10 in Q17.0Std. There seems to be no FIR .qsys file in your .rar, and thus I am using some dummy setting in my example. You may refer to the fir0.qsys in the test.zip. I have edited the test bench to feed constant data. From the Modelsim simulation, seems like I am able to get valid output from the IP as shown in the screenshot.

I have attached the ZIP of the simulation folder. You can run the simulation by doing the following:

1. Change directory in Modelsim to \test\fir0_tb\fir0_tb\sim\mentor\
2. Type "source msim_setup.tcl"
3. Type "ld" to compile
4. Type "do wave.do" to populate the waveform
5. Type "run -all" to run the simulation

You may further customize from this example with your input data as well as target configuration.

Please let me know if there is any concern. Thank you.


Best regards,
Chee Pin

alperenpalp
Novice
298 Views

Hello again

Thanks for your respose. I am going to look into it, but there is something that's confusing me about the results. The output is 7.5MSPS instead of 15 MSPS. Isn't it wrong. What am I missing here?

The reasons there is no qsys file is that I use the IP catalog directly. Should I use plaform designed instead?

Thanks.

alperenpalp
Novice
295 Views

Sink valid signal is also high during the whole simulation. I assumed I assert the valid signal every time I got a data which is at 15 MSPS, in this simulation it seems like you're feeding 60MSPS by asserting the sink valid signal for every clock cycle. What am I missing?

CheePin_C_Intel
Employee
293 Views

Hi,


Your understanding is correct. In my example simulation, the valid signal is high all the time. This example is to show working simulation and for reference only. It is not matching your test bench directly.


I am using Q17.0Std to create the example. I believe you are using QPro edition. If yes, you can use the IP Parameter Editor Pro to generate the Testbench System for your FIR II IP, and then customize from there. You may refer to my example on some of the changes required to the test bench to enable simulation.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



alperenpalp
Novice
289 Views

Hello,

I am using quartus prime lite 19.1 edition.

I am able to reproduce the results that you shared, but I am just more confused (sorry for this I am kind of new to using quartus).

My first question is the rate of the output I am seeing the output data at 7.5MSPS which matches your results. THe IP is configured to be 15 MSPS. Isn't it wrong? SHouldn't we get 15 MSPS output rate?

Secondly, I don't understand how to represent the output data. The output data is 38 bits and I want to know how to make use of it? I expect the output to be 8100h after it settles, but the output data makes no sense to me. How do I represent the data?

CheePin_C_Intel
Employee
260 Views

Hi,

Sorry if there is any confusion. Let's move to the basic mode of the FIR to ease the discussion. Then you can further customize from there.

I have create a test design with Clock Rate = Sample Rate. Then, input a pulse to the FIR IP. From the simulation, you can see the FIR output each of the coefficient in sequence which is an expected behavior. Attached is the test.zip with simulation files for your reference. You can try out on your side to verify the FIR behavior. Then, you can try with your own data.

Note that I am not sure about what should be the expected output with your input 0x8100. But after verifying the FIR is working fine with pulse, the output of the simulation should be correct. In my Modelsim simulation, I am setting the radix of my source_data = sfixed.

Please let me know if there is any concern. Thank you.

 

alperenpalp
Novice
231 Views

OK I think I understand it now.

I am sorry for bothering you with very basic questions, but I am kind of new to signal proccessing, so take it wasy on me.

I was expecting to the output value after the filter settles. I learnt about "filter gain" and now I am not confused about the output value anymore. 

I got a different confusion right now. It's about "clock rate" and "input sample rate". When I set them equal i.e 100MHz clock rate and 100 MSPS samples rate I got no problem. I get the expected value for each cycle of the clock. When I set the sample rate different, let's say 50MHz, I get always get the output at half of the input sample rate.

I attached an example or you can take a look at the screenshot. source_valid is asserted at a rate of 25MSPS.

What am I missing here?

If you want to load the modelsim example the test bench is FIR_tb and qsys file is unsaved.qsys from there you can see the configurations, and you can open the project "FIR_filter_test.mpf" I am directly using the synthesis files for the simulation.

Thanks for bearing with me.

CheePin_C_Intel
Employee
217 Views

Hi,


Glad that your initial inquiries were cleared. Regarding your latest inquiry on the sample rate, please allow me some time to look into it. I will update you on the progress by end of the week or as soon as there is any valid response. Please ping me if you do not hear from me. Thank you.


CheePin_C_Intel
Employee
215 Views

Hi,


Regarding your latest inquiry on the clock rate vs sample rate, for your information, you can refer to the "Figure 13. Time-Division Multiplexing to Save Hardware Resources" in the FIR II IP Core User Guide for further details. You would need to code additional logic on your own for the serializer and deserializer to work with the FIR II IP. When you are having higher clock rate than sample rate, you are trying to save resource required for FIR II IP. 


For example, in your case of 50MSPS and clock rate 100MHz, the FIR II IP is expecting that your serializer will serialize two data stream of 50MSPS into single data stream of 100MSPS. If you do not have the serializer and assert source_valid at 25MSPS, then you should observe your output at 25MSPS. 


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin


alperenpalp
Novice
211 Views

Thanks for your response,

I am going to get back to this, but before I do let me ask you a quick question. As you can seen in my latest screen shot I left the sink_valid signal at all times and yet I still see the source_valid signal asserted at 25 MSPS. I don't understand how it is expected.

Does the IP assume that I am feeding 2 channels when I use 2 time higher clock rate?

Thank you for being patient with me.

CheePin_C_Intel
Employee
197 Views

Hi,


Regarding your latest inquiries, as I understand it from the Figure 13. Time-Division Multiplexing to Save Hardware Resources in user guide, yes, the IP is expecting you to feed serialized data from 2 channels when your clock rate is 2x of sample rate.


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin


alperenpalp
Novice
190 Views

OK that's kind of clear for me right now.

What about the interpolation filters? I set the input sample rate to 100MSPS and clock rate to 100MHz. I get 74bits of output for every clock cycle. I assume each output value represents two samples, is that correct?

If it is true, could you tell me which part of the output is the first output? Lower part or the upper part?

Thanks!

CheePin_C_Intel
Employee
149 Views

Hi,


Regarding your latest inquiry on the interpolation Filter, I believe you are setting the Interpolation Factory = 2. If yes, for your information, the Filter will insert one 0 in between the input sample to increase the output sample rate to 2x. There is no specific info in the user guide on the mapping. However, my understanding is that the output should have 0 in between the data bit instead of splitting into upper or lower. It is recommended for you to further check out through Modelsim simulation.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin