08-10-2004 05:35 AM
Hi,Not completely tested and in AHDL for compactness (will make VHDL and Verilog versions later) but runs at around 100Mhz in C6 grade cyclone 3 stage latency 32 bit version adder is approx 470LE, mult is approx 750LE Fully parameterisable - does double precision also (10bexp, 52bit mant + sign) - NOT IEEE as I designed it to be fast! This should be all the parts needed (attached).... Regards, Steve.
08-12-2004 07:58 AM
Steve,Looks very interesting. Have you tested it as CI for NiosII ? If yes, could you share a reference design + peace of code showing the performance of your solution ? Thanks, Maga
08-12-2004 10:15 PM
--- Quote Start --- originally posted by maga@Aug 12 2004, 02:58 AM steve,
looks very interesting.
have you tested it as ci for niosii ? if yes, could you share a reference design + peace of code showing the performance of your solution ?
maga --- Quote End --- Working on that right now - will post the full project when done - just handed out the FPcore as a general IP for some to play with... Steve ...