Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
726 Views

FPADD FPMULT for NIOS + Cyclone

Hi, 

 

Not completely tested and in AHDL for compactness (will make VHDL and Verilog versions later) but runs at around 100Mhz in C6 grade cyclone 3 stage latency 

 

32 bit version adder is approx 470LE, mult is approx 750LE 

 

Fully parameterisable - does double precision also (10bexp, 52bit mant + sign) - NOT IEEE as I designed it to be fast! 

 

This should be all the parts needed (attached).... 

 

Regards, 

 

 

 

Steve.
0 Kudos
4 Replies
Highlighted
Valued Contributor III
17 Views

Re: FPADD FPMULT for NIOS + Cyclone

Hi, 

 

Ok, Ok - here a front end so it handles IEEE - sheesh. 

 

Steve...
0 Kudos
Highlighted
Valued Contributor III
17 Views

Re: FPADD FPMULT for NIOS + Cyclone

and VV

0 Kudos
Highlighted
Valued Contributor III
17 Views

Re: FPADD FPMULT for NIOS + Cyclone

Steve, 

 

Looks very interesting. 

 

Have you tested it as CI for NiosII ? If yes, could you share a reference design + peace of code showing the performance of your solution ? 

 

Thanks, 

 

Maga
0 Kudos
Highlighted
Valued Contributor III
17 Views

Re: FPADD FPMULT for NIOS + Cyclone

 

--- Quote Start ---  

originally posted by maga@Aug 12 2004, 02:58 AM 

steve, 

 

looks very interesting. 

 

have you tested it as ci for niosii ? if yes, could you share a reference design + peace of code showing the performance of your solution ? 

 

thanks, 

 

maga 

--- Quote End ---  

 

Working on that right now - will post the full project when done - just handed out the FPcore as a general IP for some to play with... 

 

Steve ...
0 Kudos