Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

FPGA Clock Pins

CLa_R
Novice
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Hi to all!
I'm working with a MAX10 FPGA (10M40SCE) and I would like if I can use the pins marked as CLKx[p/n] as normal (bidirectional) I/O pins.
 
What is the default clock pin for suppkly an external clock signal?
 
Thank to all!
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sstrell
Honored Contributor III
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They're inputs when they're used as clocks.  When not used a clock, they are GPIO (input or output).

Just try connecting them in the Pin Planner and perform an I/O Assignment Analysis.  This will verify that you are using the pins correctly.

View solution in original post

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CLa_R
Novice
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I read here at page 4:

Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

 

"Dedicated global clock input pins that can also be used for
the positive terminal inputs for differential global clock input
or user input pins. When these clock input pins are used as
single-ended pins, you can disregard the p notation.
CLK[0..7]p pins can function as regular I/O pins. "

 

What does it mean?

It is said that if the clock pin is not used as a dedicated pin, it can be used as an INPUT pin.

In the next sentence, it says it can function as a regular I/O pin.

But doesn't  "I/O" mean Input and Output?

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sstrell
Honored Contributor III
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They're inputs when they're used as clocks.  When not used a clock, they are GPIO (input or output).

Just try connecting them in the Pin Planner and perform an I/O Assignment Analysis.  This will verify that you are using the pins correctly.

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CLa_R
Novice
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Okay, I tried to create two bidirectional signals and assigned them to two clock pins in pin planner.

After compiling the project I have no errors.

But I'm still dubious, can I rest assured that it works on real hardware?

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sstrell
Honored Contributor III
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Quartus wouldn't let you compile the project successfully if it wouldn't work in hardware.

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