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FPGA Hard Memory Controller ODT Pin

Altera_Forum
Honored Contributor II
‎02-05-2015 09:54 PM
1,302 Views

We are connecting two DDR3 SDRAM ICs to a Cyclone V 5CEFA9F31. Our application only requires one ODT signal. However, there are two hard memory controller pins (T_ODT_0 and T_ODT_1). Can we use either one, or do we need to use a specific pin when we only use one signal?

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Altera_Forum
Honored Contributor II
‎02-09-2015 03:06 PM
505 Views

The dramodt section on pages 4-45 and 4-46 in the External Memory Interface Handbook Volume 3 seems to indicate that any combination of ODT[0] and ODT[1] can be configured to be asserted for CS0 and CS1. Is that correct?

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Altera_Forum
Honored Contributor II
‎10-27-2015 04:42 PM
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No one has been able to help me with this question yet. Is there anyone who can help me with this ODT pin question?

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