FPGA Stratix II Pin assignment and control panel

[Altera_Forum]

Hi guys,  

 I am using FPGA Stratix II board EP2S60F1020C3ES. I can't find the pin assignment for it also can not find the control panel .exe file to test the board   any help will be appreciated :)

[Altera_Forum]

You've provided an FPGA *part number*, not a board type. If you can figure out what board you have, then some one might be able to help. 

 For example, is this the Stratix II DSP Development Kit?  Cheers, Dave

[Altera_Forum]

Yes, it is Stratix II DSP Development Kit 

 Thanks, Mourad

[Altera_Forum]

This is the link for the Board I have 

 http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html  Thanks, Mourad

[Altera_Forum]

Since I can not provide link for the board. It can be seen on Altera website in the following sequence 

 Home > Products > Development Kits/Cables > DSP Development Kit, Stratix II Edition   Thanks, Mourad

[Altera_Forum]

Hi Mourad, 

  --- Quote Start ---   Since I can not provide link for the board. It can be seen on Altera website in the following sequence  Home > Products > Development Kits/Cables > DSP Development Kit, Stratix II Edition    --- Quote End ---    Ok, here's a design for that kit.  Keep in mind two things;  1. Stratix II devices require a Quartus II subscription edition.  2. The "ES" version of this board sucks, because the M-RAM does not work on the ES samples. (Unfortunately I have an ES version)  I see the main Altera site doesn't have much info regarding this board any more. Let me know if you want the schematic or anything else, as I probably have the CD-ROM that shipped with the kit.  Cheers, Dave  PS. I just re-read your original post and see that you have the ES device - bummer. Make sure you edit synth.tcl to change to use the ES part number.

[Altera_Forum]

Hi Dave, 

 Thanks for your help man, Really appreciated :)  Cheers, Mourad

[Altera_Forum]

Hi Dave,  

  I very new in using tcl console.  I am trying to run the synthesis script but every time I receive an error  These are the steps that I carried out:  1- I have put the four files (s2_dsp,hex_display,synth,pinout) together in one folder and called it s2_dsp  2- Created a Quartus project with name "s2_dsp" 3- In the tcl console I wrote tcl> source synth.tcl    Am I missing any steps ?   This is the ERROR that I receive each time:   source synth.tcl Synthesizing the S2-DSP 'basic' design --------------------------------------  - Creating the Quartus work directory  - Creating the VHDL files list Error:ERROR: Can't open project: s2_dsp Error: while executing Error:"project_new -overwrite "s2_dsp"" Error: (file "synth.tcl" line 64) Error: invoked from within Error:"_source synth.tcl" Error: ("uplevel" body line 1) Error: invoked from within Error:"uplevel 1 $cmd " Error: (procedure "source" line 5) Error: invoked from within Error:"source synth.tcl"    Thanks, Mourad

[Altera_Forum]

--- Quote Start ---   These are the steps that I carried out:  1- I have put the four files (s2_dsp,hex_display,synth,pinout) together in one folder and called it s2_dsp  2- Created a Quartus project with name "s2_dsp" 3- In the tcl console I wrote tcl> source scripts/synth.tcl    Am I missing any steps ?   --- Quote End ---    The zip file has a readme.txt that explains what you were supposed to do.  You did not need to create a Quartus project. The script does everything. Here's what you were supposed to do:   Stratix II DSP Development Kit 'basic' Design --------------------------------------------- 4/17/2014 D. W. Hawkins (dwh@ovro.caltech.edu) A user on the Altera Forum asked about the pinout for this board. I created this stripped down 'basic' design from my code repo. The design was synthesis tested using Quartus 12.1sp1 subscription edition. There is no SDC file for this project, so Quartus generates a warning. To synthesize the design; 1. Unzip this file eg., c:/temp/s2_dsp_basic 2. Start Quartus and select the Tcl console (make it visible with View->Utility Windows->Tcl Console) 3. Run the synthesis script tcl> cd c:/temp/s2_dsp_basic tcl> source scripts/synth.tcl Synthesizing the S2-DSP 'basic' design -------------------------------------- - Creating the Quartus work directory - Creating the VHDL files list - Applying constraints - Processing the design - Processing completed NOTE: The earlier version of this kit shipped with "ES" devices (engineering samples). The synth.tcl script assumes you have a production device (non-ES) .Edit that script if you have an ES board. Enjoy! Cheers, Dave   Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Sorry, it might be a silly question from me but how can I access the synthesis file without showing Quartus software the right directory.  because if I just follow the steps in the readme.txt file I will get this error and I don't know how to reach the correct directory in Quartus software   source scripts/synth.tcl Error:couldn't read file "scripts/synth.tcl": no such file or directory Error: while executing Error:"_source scripts/synth.tcl" Error: ("uplevel" body line 1) Error: invoked from within Error:"uplevel 1 $cmd " Error: (procedure "source" line 5) Error: invoked from within Error:"source scripts/synth.tcl"    Thanks, Mourad

[Altera_Forum]

--- Quote Start ---   Sorry, it might be a silly question from me but how can I access the synthesis file without showing Quartus software the right directory.   --- Quote End ---   Sorry, my bad, I did not include one instruction - change directory using the Tcl console. See the readme.txt inlined above.  Please download the zip file again, I modified the synth.tcl script slightly to work properly under 13.0sp1 (the last version that supports Stratix II devices).  Cheers, Dave

[Altera_Forum]

Hello everyone. 

I got a Stratix II EP2S60 DSP Development Board, but I couldn't find the cd-rom which contains the software of the development kit. Am i lucky enough to find anyone here having it and willing to send me a copy? my email is steeqa@gmail.com. Thanks and thanks.