Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21602 讨论

FPGA Timing contrains books/Training Course/Online lesson feebacks

Altera_Forum
名誉分销商 II
1,125 次查看

Hi, 

 

I have several projects timing sensitive regarding code modifications (Stratix IV, Arria V GX). I would like to improve my timing contrains knowledges to avoid recompilation problems. 

 

I am looking for advanced information, I have already read plenty of AN or user messages on forums. 

So it would be great to have feedbacks/recommendations about training courses / books / etc. For example: 

- Altera "Advanced Timing Analysis with TimeQuest (IDSW125), 8 hours" 

- Doulos 5 days "Advanced Altera Designing with Quartus" 

Online training is more easy for me but I can travel (based in Germany near Karlsruhe). I am looking for English (or French) lessons. 

 

FI I often use: 

- LVDS inputs (20 to 80 inputs up to 1000Gbps) 

- transceivers in TX or TX/RX modes (3 to 6Gbps) 

- DDR2 and DDR3 interfaces with custom or Uniphy IP. 

 

Thank you in advance.
0 项奖励
0 回复数
回复