We are migrating from Cyclone 4 with EPCS to Cyclone 10 with EPCQ. Until now with the first FPGA the startup time until the Nios2 softcore was launched was about 300ms. But now with the new Cyclone 10 FPGA this time is about 800ms.
Is it possible to investigate why Cyclone 10 LP family takes so long time to boot NIOS?
To measure the Nios startup time, we move an output IO in the first softcore instruction.
We have also been looking at the communication SPI between the FPGA and the EPCS and EPCQ memories (in the Cyclone 4 and 10 respectively). We can see that the configuration process is done in two reading blocks, after seeing the DQ1 signal. In the first one, the HW of the FPGA is configured and in the second one, the SW program is copied to the RAM (on-chip memory).
We have seen that the first part always lasts more or less 90ms, but the second part varies. With the EPCS memory, the SW copiing task takes another 90ms but the same process in the EPCQ takes about 800ms.
We have also noticed that the SPI clock stops moving when the reading process in the EPCS is finished, but it keeps changing the state in cyclone 10 with EPCQ.
1) Booting SPI process with Cyclone 4 & EPCS:
2) Booting SPI process with Cyclone 10 & EPCQ:
The blue signals refers to DQ1 data output from memory and the green one refers to CLK from FPGA to memory.
Hi Xabier ,
My apologize for the delay on answering ,