FPGA or CPLD?

[Altera_Forum]

We have a design that we would like to fit in a CPLD or FPGA, we have extremely limited experience with both technologies, and need help to determine which technology and which part in the particular technology would be suitable. I have attached block diagrams to accompany the following description, the block diagram show two possible ways of implementing what we need.  

 What we need to implement in the CPLD or FPGA is:   16 counters of 18 bits each that can count at a rate of 1 MHz. Logic to provide a serial bus to read the 16 counters. The ability to read the previous counter results while new counting is occurring, (i.e. latches). We need a very small package (footprint) And as low power as is possible. The attached pdf will give more insight to the requirement.   Your assistance is appreciated.:confused:

[Altera_Forum]

you can try and synthesize directly in a cpld (many to choose from) to see how it fits. I believe a small cpld will do.

[Altera_Forum]

when you do the synthesis do you have to select the device first or can you synthesize the design and have the tool recommend parts that the design will fit in?

[Altera_Forum]

I will start with smallest.  

The tool does give you options but I haven't checked that

[Altera_Forum]

notice also with cpld you don't need additional programming device (or flash) to hold the bit stream

[Altera_Forum]

Hi Kaz, 

 thank you for responding to my post, I appreciate it. How would I estimate the power consumption of the operating CPLD?

[Altera_Forum]

--- Quote Start ---  Hi Kaz,  thank you for responding to my post, I appreciate it. How would I estimate the power consumption of the operating CPLD?  --- Quote End ---    There is a tool "Power play power analysis" under processing menu. It requires you first compile then run the tool either on a percent toggle rate or actual simulation data. The toggle rate may be enough if you enter the average. clock is taken as 200%, half clock as 100%, 1/4 clock is 50% and so on. Each counter bit can thus be estimated then all averaged.

[Altera_Forum]

actually the default toggle rate of 12.5% is that of a 16 bit counter. 

 here is altera help: Enter the average percentage of logic toggling on each clock cycle. The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. To ensure you do not underestimate the toggle percentage, you can use a higher toggle percentage. Most logic only toggles infrequently, and hence toggle rates of less than 50% are more realistic

[Altera_Forum]

Hi, 

 You can use a MAX3000A if you absolutely need 5v compatible I/O. Otherwise you can go with MAX II or MAX V. Pick the largest size part when you do the design setup in Quartus II (free web edition). After compilation you can see the percentage of resources used. You can change the project to a smaller device in the project settings (without recreating the project). Altera also just came out with MAX10 fpga (single chip solution). They are not as inexpensive as the older MAX devices though.   I think the older MAX3000A is not supported in the latest version of Quartus II (v14 or v14.1) so stay with v13 or so. I dunno about the MAX II or V because I've never used them.  I hope that helps.