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FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Steve-Mowbray-ENL
New Contributor I
1,658 Views

Hi

In passive serial configuration the Linux platform powers on and is booted with FPGA in unconfigured state -- our RBF file is then configured via passive serial and working but is not detected as a PCIe connected device in Linux -- the command "echo 1 > /sys/bus/pci/rescan" has no effect...

Is there a user guide or instructions anywhere as to how to establish the PCIe connection in Linux after passive  serial configuration

Thanks

Steve

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1 Solution
Wincent_Altera
Employee
831 Views

Hi Steve,

Thanks for your confirmation, I will transition this support thread to community.
I saw corestar have reply some workaround, perhaps you may refer to that and see if that able to help you or not.

Any time in future, if you having any problem, you may file a new thread.
Someone will be there to support you. If you need my support on PCIe IP, please mention my name "Wincent" so that this will route to my support Q.

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Altera

p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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28 Replies
Wincent_Altera
Employee
359 Views

Hi Steve,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

 

Regards,

Wincent_Altera

p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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Steve-Mowbray-ENL
New Contributor I
343 Views

Hi Wincent

Yes please close this ticket -- we are following up on Linux community since is specifically a Linux issue pertaining to FPGA...

Regards

Steve 

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Wincent_Altera
Employee
832 Views

Hi Steve,

Thanks for your confirmation, I will transition this support thread to community.
I saw corestar have reply some workaround, perhaps you may refer to that and see if that able to help you or not.

Any time in future, if you having any problem, you may file a new thread.
Someone will be there to support you. If you need my support on PCIe IP, please mention my name "Wincent" so that this will route to my support Q.

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Altera

p/s: If any answer from the community or Altera Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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FvM
Honored Contributor I
565 Views

Hi,
in my view it's unwanted to get the FPGA reconfigured unconditionally during PC reboot. This should only happen on power-on reset or explicite request. I can confirm that evaluation boards like Terasic Arria TR10a-HL are keeping FPGA configuration during PC reboot.

This allows to check if the initial PCIe device enumeration works with your design.

You previously mentioned you are not sure if NCONFIG is triggered in your hardware during reboot, but it should be easy to find out, e.g. by loading a test configuration over JTAG.

Does the remove/configure/rescan sequence work for your with other configuarion methods, e.g. JTAG or AS?

Regards
Frank

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Steve-Mowbray-ENL
New Contributor I
545 Views

Hi Frank

  •  "Does the remove/configure/rescan sequence work for your with other configuration methods, e.g. JTAG or AS?" 
    • yes when we do an AS build and load the FPGA flash device with resulting JIC and also change the MSEL pins the FPGA PCIe device is enumerated and we can remove/rescan at will -- we can also change the MSEL pins while still running then do a passive serial write of our passive serial build RBF and remove/reset/rescan the PCIe devices into a working condition -- but what we want is power on in PS mode and do the FPGA configuration that way 

you mention the Terasic Arria TR10a-HL -- does that run with PC Linux and if so what is the sequence to rescan the PCI device when the FPGA is configured?

Regards

Steve

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corestar
New Contributor I
296 Views

Hello @Steve-Mowbray-ENL ,

I had the exact same problem. On a Raspberry Pi CM4, the solution outlined in the following link works by  PeartreeStudios:

 

PCIe Hot Swap 

 

The "rescan" idea does not work as you discovered. I have two scripts.

 

bind_pci contains:

 

echo "Bind PCIe Driver"
sudo bash -c 'echo fd500000.pcie > /sys/bus/platform/drivers/brcm-pcie/bind'

 

and unbind_pci  contains:

echo "Unbind PCIe Driver"
sudo bash -c 'echo fd500000.pcie > /sys/bus/platform/drivers/brcm-pcie/unbind'

 

These are clearly system dependent. But each time I update the FPGA firmware:

  1. Run unbind_pci if it was already bound
  2. Update the firmware via PS or JTAG
  3. Run bind_pci.

 

 

 

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Steve-Mowbray-ENL
New Contributor I
240 Views

Thank you corestar will try this out

Regards

Steve

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Scarletios
Beginner
35 Views

<p>It seems the FPGA isn't being detected as a PCIe device after passive serial configuration. To resolve this, ensure the correct PCIe drivers are installed and verify the device tree setup if using embedded Linux. You might also want to manually trigger a rescan and check the FPGA vendor's documentation for specific instructions on setting up PCIe detection. If the issue persists, contacting the FPGA manufacturer's support could provide further guidance.</p>

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