Re: FPGA retriggerable monostable multivibrator?

Altera_Forum · ‎02-26-2015

Does anyone have circuit design for making a retriggerable monostable multivibrator on the FPGA? Typically, these use a capacitor that gets dumped. Thoughts?

Altera_Forum · ‎02-27-2015

The simplest way to do something like that is with a counter. Something like this maybe?


localparam MAX_COUNT = 8'b1110;
reg out;
reg  counter = MAX_COUNT;
always @ (posedge clock) begin
  if (trigger) begin
    counter <= 8'b0;
    out <= 1'b1; //out is set on trigger
  end else if (counter != MAX_COUNT) begin
    counter <= counter + 8'b1;
  end else begin
    out <= 1'b0; // out is cleared after count
  end
end

Obviously you could change the size of the counter, the polarity of the out signal, and the MAX_COUNT (which could even be another register if you want to change it during run time).

The counter is essentially acting as the capacitor in this case, counting up (charging), until some threshold after which the output clears.

Altera_Forum · ‎02-27-2015

--- Quote Start ---

The simplest way to do something like that is with a counter. Something like this maybe?


localparam MAX_COUNT = 8'b1110;
reg out;
reg  counter;
always @ (posedge clock) begin
  if (trigger) begin
    counter <= 8'b0;
    out <= 1'b1; //out is set on trigger
  end else if (counter != MAX_COUNT) begin
    counter <= counter + 8'b1;
  end else begin
    out <= 1'b0; // out is cleared after count
  end
end

Obviously you could change the size of the counter, the polarity of the out signal, and the MAX_COUNT (which could even be another register if you want to change it during run time).

The counter is essentially acting as the capacitor in this case, counting up (charging), until some threshold after which the output clears.

--- Quote End ---

Awesome thanks! I will definitely try out this design. I have been looking for a method that doesn't require a clock, but I think this might work. It just limits the "values" of the "capacitance" to# clock cycles, meaning it can't have a of 1.32124 clock cycles as the "charge time".

Thoughts?

Altera_Forum · ‎03-03-2015

You just have to make your clock fast enough for the resolution you want. For example a 100MHz clock would give you 10ns resolution - do you really need more than that for your project?

FPGAs like clocks, its what synchronises everything together. While it would be possible to replace (posedge clock) with *, I really wouldn't recommend it as who knows what would happen as it would be very likely that your counter would start developing funny glitches (if it works at all) as each bit of it may have slightly different propagation delays from another.