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FPGA to Host PCIe Latency Calculation

Honored Contributor I

Hello All, 

We are working on a project where we are processing 10G Data in FPGA and forwarding the processed data to linux host via PCIe for further operations. As our requirement is to implement low latency operation, calculating end-to-end latency numbers are essential. We could able to capture hardware delay with some internal timstamp modules. But we are stuck in PCIe space. The last possible trigger that we could able to access in hardware was DMA operation done status (of V-series Avalon-MM DMA for PCIe), which ideally indicates that DMA processed the data for corresponding descriptor. 

But we need to have a trigger to know when the sent data reached user space in linux host. Standard approach is PTP, but implementation is bit tricky and we don't have much time spend on it. 

Anyone here ever tired calculating FPGA to Host latency or have any simpler approach/workaround, will be very helpful. 


Thanks in Advance :)
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