Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

FPGA utilization

Altera_Forum
Honored Contributor II
1,087 Views

hi can we use all the user I/O's in the FPGA? If so what wiill happen??????????

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
408 Views

In general you can use all User I/Os, although there may be placement restrictions such as different Bank IO Voltage, dedicated functionality, Dual purpose pins for programming etc. 

 

Enter your pinning in Quartus II and compile your design to validate it.
0 Kudos
Altera_Forum
Honored Contributor II
408 Views

 

--- Quote Start ---  

hi can we use all the user I/O's in the FPGA? If so what wiill happen?????????? 

--- Quote End ---  

 

 

 

Why not? Pins are made to be used in design, what's the other purpose they could have? :)
0 Kudos
Reply