FPGA won't load from flash which contains hardware and NIOS software image

[Altera_Forum]

Set up is Cyclone3 with epcs128 serial flash. My FPGA includes the NIOS and epcs_controller. 

 Using the Convert Programming Files tool, I covert my .sof file into a .jic file and then program the serial flash with the Quartus Programmer. After reset, FPGA is loaded correctly (I can see conf_done go high) from the flash.   Now, I try to create another .jic file that includes both the .sof file and the NIOS .elf according to the instructions  altera.com/support/kdb/solutions/rd12092009_471.html   However, when I program this new .jic, the FPGA won't load (conf_done does not go high).   Any help is most welcome!

[Altera_Forum]

i haven't had luck with that solution either, try the instructions at the Nios Wiki on part 3. sof in EPCS, program in EPCS: 

 http://www.nioswiki.com/index.php?title=operatingsystems/uclinux/flashprogrammer

[Altera_Forum]

@thepancake 

 Thanks for the suggestion. The suggestion in part 3 is to program an .sof which has an epcs_controller to the FPGA, and then use that FPGA to program the new image to the the EPCS. This is also carried out using the Nios II Flash Programmer GUI. I tried this through the GUI and I am able to program the .elf and .sof file to the epcs flash, but again on power reset, it doesn't seem to load the FPGA from the flash properly as there is no conf_done.

[Altera_Forum]

oops the solution wasn't the one i was thinking of after all 

 try following the instructions from the solution but only including the hw.hex in your .jic file. it seems like the sw.hex is being put at the beginning of the EPCS causing the FPGA to fail configuration

[Altera_Forum]

I thought about that too, and I tried adding only the hw.hex to the .jic file... but I get the same problem, no conf_done after reset. However, if I go straight from hw.sof to .jic using the Convert Programming Files GUI... I don't have that problem as mentioned in my initial post. 

Did your suggestion work for you?

[Altera_Forum]

i have gone through some headaches when using hex files in the convert programming files menu (with the addressing). i'll try and duplicate your issue later in the week

[Altera_Forum]

I tried the procedure (altera.com/support/kdb/solutions/rd12092009_471.html 

) using an Arria2GX device... and it works. However, when I try it on cyclone iii it fails (no conf_done). Something funny with the cyclone iii?

[Altera_Forum]

Solved. 

The instructions to create a .jic file from a sof and elf file are correct. It turns out to be a hardware issue. There was a capacitor on the conf_done signal which when we removed, the fpga would boot from flash upon power reset. The capacitor was put in to remove noise from the conf_done because conf_done was used as a trigger to cause a reset to our FPGA. Anyways, it seems the capacitor prevented conf_done from going high fast enough to signal the FPGA that it was finished configuration and cause the FPGA not to boot.