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Altera_Forum
Honored Contributor I
847 Views

FPP Configuration, Bank 2A and reuse

Is it possible to reuse configuration pins (e.g. FPP) during User Mode? We have a 16-bit parallel bus to FPP-configure the FPGA from a Host and want to reuse the same 16-bit bus during User Mode (for Host to FPGA comms). The pins are multi-purpose pins in the C10GX and thus available during User Mode. 

 

However: 

 

Section 5.7.8 of C10GX51003 2017.11.10 (Guideline: Usage of I/O Bank 2A for External Memory Interfaces) advises: 

"Do not use I/O bank 2A's pins that are required for configuration-related operations as external memory interface pins, even after configuration is complete. For example: 

— Pins that are used for the Fast Passive Parallel (FPP) configuration bus" 

 

Could someone perhaps explain what is meant here exactly? 

 

Why would the above document caution against this (re)use of the configuration bus? In contrast to this, pcg-01022 2017.06.21 (Cyclone 10 GX Device Family Pin Connection Guidelines) says about the DATA[31:1] pins: "These pins can also be used as user I/O pins after configuration.", yet re DATA0: "You can use the DATA0 pin for PS or FPP configuration scheme, or as an I/O pin after configuration is complete." 

 

Runtime reuse of the FPP configuration bus seems logical given the size of the 16-bit bus that is already dedicated between the Host and the FPGA for the FPP configuration function. Is this possible?
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3 Replies
Altera_Forum
Honored Contributor I
41 Views

I think what you're proposing is absolutely fine. Indeed, not being able to do this seems extremely restrictive and would clearly result in a large number of duplicate pins being required on both devices. 

 

The restriction refers to hosting external memory from the FPGA. This differs from what you're proposing (I think) whereby you intend to host the FPGA (as a memory mapped slave peripheral) from the host. 

 

The guidelines indicate you should refer to the pin-out file for more info regarding configuration. However, this doesn't seem to indicate any restrictions. 

 

I'm a little perplexed as to the point of this apparent restriction. However, in your case I don't think it's relevant. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
41 Views

Hello Alex, thank you for your positive response. Correct, the FPGA will be operated as a memory-mapped peripheral by the Host in User Mode. 

 

Even if the Guideline should refer only to the hosting of external memory from the FPGA, I agree that also in this case the Guideline is perplexing, and it does seem quite adamant. Would it be possible to clarify this with the design team, perhaps?
Altera_Forum
Honored Contributor I
41 Views

 

--- Quote Start ---  

Would it be possible to clarify this with the design team, perhaps?  

--- Quote End ---  

You can always try putting a basic FPGA design together to prove you can realise a fit when using these pins as bi-directional pins in user mode. I don't see you having any trouble with that. 

 

Thinking about the case where you host external memory from these FPGA pins - the scenario the documentation suggests isn't supported - this sounds somewhat compromised anyway. You boot your FPGA from this external memory device and then give your FPGA direct access to it, potentially allowing you to overwrite your boot image. Yes - disciplined operation could avoid that. However, if this was deliberate - allowing you to upgrade the FPGA's boot image - and something failed (e.g. power), then you render your system useless. I can't see that this is the reason for this limitation but it's an issue worth avoiding. 

 

Cheers, 

Alex
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