Hi,I have a flip flop in my fpga which is driving output pins (reg to output path). The clock of this is 5ns and the one outside fpga is 5ns (phase shifted by 90). The phase shifted clock is generated using a PLL to feed a circuit outside the fpga. When I give set_output_delay for my output ports, I find that there is setup violation and the main reason for it is the clock network delay which is around 2.3 ns. And when I run the timing closure recommendations, I see that an intra domain skew is the reason for the setup violation. Clock transfer as per timequest is clock_4(clock name mentioned in the timequest) but I don't have any such clock in the design. I have tried promoting it to global clock which Quartus doesn't consider as it is unknown. How can I reduce the intradomain skew in such case? Also, how can I reduce the clock network delay? Thanks
I'm a little confused about the clock to the "downstream" device. Are you saying it is generated by an FPGA PLL that is introducing a 90 degree phase shift from the one used for the output register (so the latch clock is 1 cycle plus 90 degrees (1.25 ns) later? Sounds like you might need multicycle. Can you post the waveform view report of the failing path and your .sdc?
Hi sstrell,The understanding by you is correct. For the flip flop within the FPGA, it is a 5ns clock and for the one outside the FPGA , it is the same 5ns but with a phase shift of 90. The following are the constraints on the output ports. I have created a virtual clock for the output delay. create_clock -name emif_clk -period 5 set_output_delay -clock emif_clk 4.5 [get_ports LC0] set_output_delay -clock emif_clk 4.5 [get_ports LC1] set_output_delay -clock emif_clk 4.5 [get_ports LC2] I have attached image of the waveform as shown in timequest GUI.
I'm still a little confused. If a PLL in the FPGA is generating both of these clocks, your .sdc should look something like this:# internal clock that drives the output register create_generated_clock -name output_clk -source <PLL_input_clock_pin> <relation_to_source> <PLL_output_clock_pin_1> # output clock to drive downstream device create_generated_clock -name emif_clk_int -source <PLL_input_clock_pin> <relation_to_source> -phase 90 <PLL_output_clock_pin_2> # extra generated clock to define clock coming out of FPGA going to downstream device create_generated_clock -name emif_clk -source <PLL_output_clock_pin_2> -multiply_by 1 <FPGA_clock_output_port> # false path so data analysis is not performed on output clock set_false_path -to <FPGA_clock_output_port> # output delays; you need to have separate max and min delays set_output_delay -max -clock emif_clk 4.5 [get_ports LC0] set_output_delay -min -clock emif_clk <min_value> [get_ports LC0] set_output_delay -max -clock emif_clk 4.5 [get_ports LC1] set_output_delay -min -clock emif_clk <min_value> [get_ports LC1] set_output_delay -max -clock emif_clk 4.5 [get_ports LC2] set_output_delay -min -clock emif_clk <min_value> [get_ports LC2] # multicycle so correct latch edge is used set_multicycle_path -from output_clk -to emif_clk -end -setup 2 Let me know if this matches your design, which is still unclear.