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Altera_Forum
Honored Contributor I
753 Views

FPP Configuration Timing: Clock Stop = high

We would like to configure a Cyclone V GX C5 using FPP via a TI DSP's EMIFA (External Memory Interface) bus (in Asynchronous mode). VC-52007 2015.12.21 Figure 7-3 mentions in note (5): If needed, pause DCLK by holding it low. 

 

Question 1: Is this clock pause option also applicable to Figure 7-2, i.e. when the DCLK-to-DATA[] Ratio (r) = 1? 

 

Question 2: Would it also be OK to pause DCLK by holding it high? 

 

If so, we would want to connect the TI DSP EMIF's EMA_nWE (Write Enable) strobe to the Cyclone's DCLK pin, which would result in an unbalanced DCLK signal high for 20ns and low for 6.5ns, occasionally held high in the inactive state. 

 

Any comments on the feasibility hereof, please?
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2 Replies
Altera_Forum
Honored Contributor I
17 Views

The important bit here is that there are no 'maximum' values specified for 'DCLK high time', 'DCLK low time' or 'DCLK period'. The passive programming methods are entirely synchronous, clocked by DCLK. Run and pause it as you wish. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
17 Views

OK, thanks!