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Altera_Forum
Honored Contributor I
824 Views

MAX10 watchdog use // which version Quartus?

I want to use for new project first time MAX10 FPGA so some of my questions may look "primitive" ... 

 

I read that Quartus Prime is needed - today's version is 16.0 but it only offers to install Aria10, I can not see MAX10 support. As Aria10 support needs tens of GB to be installed I decided to go back to version 14.1 where 

MAX10 support first appears. It is only about 300MB package support to be installed for 14.1 . But it says it is not (?) Quartus Prime 16.0 but Quartus II 14.1 

 

There is inside MAX10 also watchdog that must be disabled (if not used) by first time erasing whole chip. I read a lot of docus but I can not find any information how to kick this watchdog from FPGA. What I only found is that IP for 

remote update includes inside already support to handle watchdog during upgrade. Another info I found is that MAX10 is AVALON BUS ready. It seems that watchdog is implemented in AVALON MM bus. (memory mapped) 

I do not know yet how to work with this AVALON BUS but it is not an issue now. 

 

There is no support (any IP block) in Quartus II 14.1 to handle watchdog. At least I can not find it. I have not installed Quartus Prime 16.0 yet as I am even not sure MAX10 support is there as it is not offered for download, just for Aria10. 

 

What I am overlooking? How to handle watchdog for MAX10 from FPGA? What software (IP) I need for this? 

 

thank you
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2 Replies
Altera_Forum
Honored Contributor I
33 Views

The 'standard' and 'lite' editions of Quartus 16 support MAX 10. Download it from the download center (https://www.altera.com/downloads/download-center.html). 

 

The watchdog issue you refer to, that requires erasing the device prior to programming, has been fixed in production silicone. So, unless you want the watchdog functionality (or you have very old pre-production silicone) you can ignore this issue. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
33 Views

SOLVED:  

 

Version 14.1 is also OK. 

There is DualConfiguration IP Core in Basic functions -> Configuration Programming in IPs 

On page 5-2 of UG-M10CONFIG pdf is table what to write to reset watchdog .... 

 

All info above perfectly fits together with altera_dual_boot component from IP library: address is 3bit wide, data r/w is 32 bit wide /see attached picture/ 

 

It needed a bit of more reading and today is everything clear comparing to yesterday :) /night rest is always needed/