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Altera_Forum
Honored Contributor I
1,256 Views

Facing problems in constraining Negative Setup Slack

Hello all, 

 

I am facing problems in constraining Negative Slacks (for a 50Mhz clock and 150MhZ clock both generated clocks). I had a negative slack of -59 which was because of using a 44_24 LPM divider which I solved using 2 stages of pipeline. There were few other slack issues which I constrained using set_clock_groups and a set_false_path.  

 

Now, I have setup negative slack of -14 and -6 (two different generated clocks) within a module where the input to the module comes from a written register(in SW), using which a division is performed and the value is stored in a register. The same happens with one more module. I am not sure why lot of timing issues come up with Division (Be it using lpm or a simple arithemtic division). 

 

I am quite new to Timing analysis, that I am not sure if I should alter the code which can solve the timing issues or use constraints set_false_path / multicycle paths / setting max delays to ignore the timing analysis. I dont want to alter the code much which has been already tested.  

 

I am attaching the Setup Timing Closure Report, the Source code of the module and the SDC File. 

 

Looking forward to your suggestions! Thank you.
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7 Replies
Altera_Forum
Honored Contributor I
184 Views

If you have a timing problem you can solve it editing design files or if violation is small (ex. 0.5 ns) changing optimization parameters or trying design space exploration (multiple compile seed).

Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

If you have a timing problem you can solve it editing design files or if violation is small (ex. 0.5 ns) changing optimization parameters or trying design space exploration (multiple compile seed). 

--- Quote End ---  

 

Yes, I have tried optimizing using the Timing optimization advisor. It has not helped much. I still get a lot of unconstrained paths with a high negative setup slack. I dont have a DSE to perform Design Space Exploration.
Altera_Forum
Honored Contributor I
184 Views

If slack is high you have to lower your frequency or add pipeline stages into your design.. no way to escape.. 150 MHz is an high frequency for an FPGA and circuit need to be carefully designed. 

DSE is included into Quartus installation but can't solve 14ns violation.. 

 

Division is very slow.. maybe you need more latency?
Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

If slack is high you have to lower your frequency or add pipeline stages into your design.. no way to escape.. 150 MHz is an high frequency for an FPGA and circuit need to be carefully designed. 

DSE is included into Quartus installation but can't solve 14ns violation.. 

 

Division is very slow.. maybe you need more latency? 

--- Quote End ---  

 

 

Yes. I made the division faster by changing the logic. The setup slack for the System Clock (50MHz) is fine now. But the one with 150MHz is still lagging. Could you please look into the source code and let me know if Im missing something. The Timing report for it is also in the attachments. Thanks a lot!
Altera_Forum
Honored Contributor I
184 Views

It is need entire project because timing depend on a lot of things (device, pinout, etc..) but I don't think I have enough time to do your project analysis now. Use Timequest to find what path are failing and then edit design.. 

You use C8 device.. maybe you can upgrade to a faster speed grade? 

Another way is to change phase shift to improve setup times..
Altera_Forum
Honored Contributor I
184 Views

 

--- Quote Start ---  

It is need entire project because timing depend on a lot of things (device, pinout, etc..) but I don't think I have enough time to do your project analysis now. Use Timequest to find what path are failing and then edit design.. 

You use C8 device.. maybe you can upgrade to a faster speed grade? 

Another way is to change phase shift to improve setup times.. 

--- Quote End ---  

 

 

Thanks a lot! Will try it. But will setting up a lateny be helpful here?  

 

-6.109(Setup slack) ; APP-FPGA_Application_Logic:inst1|FilCtrl:inst30|PWM_Gen:inst1|\PWMControl:v_pulse_count_nom[0] ; APP-FPGA_Application_Logic:inst1|FilCtrl:inst30|PWM_Gen:inst1|\PWMControl:v_updatePWMvalue ; 150Mhz_Osc_Clock ; 150Mhz_Osc_Clock ; 6.666 ; 0.369 ; 13.145 ; 

 

Is setting up a latency for the specific target a good idea? Will it help? If it is, what is the SDC command to set up latency for the specific target? I tried with different Tcl commands to specify target but didnt work.
Altera_Forum
Honored Contributor I
184 Views

If you want to change latency of divider IP you need to change your design.. also if you insert registers between path you have to edit your design.. there is no simply way to solve it. 

With SDC you can ignore timing failure but just ignore (false_path command).. then your design may not works. Also multicycle.. is like ignoring if your design don't consider it.
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