Final year project question, PCIe interface to GPIO?

Altera_Forum · ‎10-08-2014

Hello everyone,

My group members and I are starting our final year project for computer engineering this week and I have a question about PCIe data transfers to the FPGA.

We are provided with an Altera DE2-70 or DE2-115. We worked with these baords before and are familiar with a lot of their features. What we are not familiar with is the GPIO. We plan to use the DE2-115 and for our application we need to transfer a lot of data to and from the board very quickly. We originally considered using the Gigabit Ethernet on the board however we are afraid it will be insufficient and we will data-starve the board. We are now considering using PCIe from the host computer but our boards do not have a PCIe interface. So the current idea is to get a PCIe riser cable, chop it up, and make a connector to the DE2s GPIO. Ultimately, can this be done? Can we go from PCIe to GPIO (i.e. through the use of some free libraries)?

Another question is we plan to use OpenCL to communicate with the board. Would this PCIe -> GPIO still be supported in OpenCL? We have no problem writing our own kernel and are not tied to using the provided altera SDK.

Altera_Forum · ‎10-08-2014

Sorry, two of your ideas will not work;

PCIe support requires specialized transceivers that do not exist on these boards.
OpenCL support is specific to a small range of latest-generation boards.

But 1GbE might be ok - at least the kits support that.

What is the data rate you need to achieve to your host PC?

Cypress just released their EZ-USB FX3 kit

http://www.cypress.com/?rid=99916

This $49 kit has a USB 3.0 controller on it, and should provide >100MB/s transfers (depending on your PC).

The kit can be interfaced to the HSMC connector on the DE2-115 via an HSMC adapter board

http://www.cypress.com/?rid=99922

which is also $49 (although when I ordered my kit, I just requested this board, and they sent it to me).

The kit already comes with Altera interface examples. I haven't tested them yet, but I will, so if you decide to go this route and get stuck, you can ask for advice.

Cheers,

Dave

Altera_Forum · ‎10-08-2014

Okay thanks for letting us know before we started.

The USB 3.0 connection is interesting, we will explore the idea.

The data rate we need to achieve is variable however the more the merrier. We have a design that requires 128 bits to be read from the host every clock cycle for every computational core that we have and we plan to run the fpga at 100Mhz. that equates to 128Mb/s/core. For starters we will be impleming one core as a proof of concept so the 1GbE is entirely sufficient however once that is running we were hoping to make multiple cores. the 1GbE will limit us to 8 cores before we run into data starvation. Ideally we would like more than 8 cores which is why we were looking to explore other options.

Thanks for your reply,

Dmitry

Altera_Forum · ‎10-08-2014

--- Quote Start ---

For starters we will be impleming one core as a proof of concept so the 1GbE is entirely sufficient however once that is running we were hoping to make multiple cores. the 1GbE will limit us to 8 cores before we run into data starvation. Ideally we would like more than 8 cores which is why we were looking to explore other options.

--- Quote End ---

I would recommend ignoring the limitation of 1GbE, and talk with your advisor about the following option;

1. You implement the 8 cores and show that the system works, and that 1GbE is sufficient.

2. You implement more cores in the FPGA, and allow the 1GbE interface to select a subset of 8 cores.

At that point you will have shown that your FPGA resources are sufficient to implement +8 cores, but due to interface issues, you cannot stream more than 8 cores.

Don't bother getting distracted by the Cypress chip at that time. I won't of course take my own advice, and will get distracted by it ... :)

Cheers,

Dave