Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Finding Dmax and Dmin

Altera_Forum
Honored Contributor II
1,083 Views

how to find maximum data delay and the minimum data delay(excluding pin delays) in quartus II 8.0 ?

0 Kudos
0 Replies
Reply