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Hello friends,
I'm currently working with ALTERA DE2-115 board. I need to know the internal registers of this board's PHY. The PHY is Marvell 88E1111. After searching, I found a product brief. But it hasn't mentioned the map of the registers. Has anyone experienced this? Thanks in advanceLink Copied
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Are you sure 88E1111 has internal registers? This document:
http://smartdata.usbid.com/datasheets/usbid/2008/2008-q4/88e1111.pdf show a block diagram and there are no internal registers. The external signals controls the operation of the PHY.- Mark as New
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Thank you my dear friend for your answer,
Yes I'm sure. but if you look at it exactly,you'll find it.- Mark as New
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The registers are described in the data sheet, however, access to the 88E1111 data sheet requires an NDA with Marvell.
Cheers, Dave- Mark as New
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Yes i know that,
I wanna know what if someone hadn't that NDA. I mean isn't there any other source? what Should "I" do? :D- Mark as New
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--- Quote Start --- Yes i know that, I wanna know what if someone hadn't that NDA. I mean isn't there any other source? what Should "I" do? :D --- Quote End --- NDA = non-disclosure, which means that you're not meant to share. You need to get your own version, i.e., contact Marvell. You could probably also look in the Linux source for the Marvell device driver. That will tell you most of the register settings. I believe a lot of them are generic between 1GbE PHYs. Cheers, Dave
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Thanks dear Dave,
I checked it. But Unfortunately Marvell doesn't support in my country. What are Linux sources for Marvell?Can you explain a bit more?- Mark as New
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--- Quote Start --- What are Linux sources for Marvell? Can you explain a bit more? --- Quote End --- Many of the Terasic boards contain 1GbE PHYs. Look at their NIOS II Linux source code. The code may not explicitly look like its talking to a Marvell PHY, however, whatever code is talking to the PHY via the MDIO bus must be accessing registers that you can also use. Cheers, Dave
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Which register to you need to access, change?
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Thank you dear fpgaengineerfrankfurt ,
I found the datasheet and I wrote a code which is able to write/read to/from the PHY. I needed to change the MAC speed in register 20.6:4 to 100 Mb/s.- Mark as New
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Do you know about the built in feature called :"Packet Generator"?
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Do you only read PHY registers (MDIO?) or also ethernet data directly ?
>Do you know about the built in feature called :"Packet Generator"? Yes, it is activated by setting some bits in a certain register. I tried that recenctly in a xilinx system but did not succeed. I am about to repeat this on my Altera board now.- Mark as New
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I'm currently working on MII (Media Dependent Interface) for receiving data packets.
Exactly...I have the same problem.I mean I set the mentioned bits for activating this Packet Generator, but nothing happened.- Mark as New
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My problem was that I did not know about the reserved bits, I have to maintain. When reading back the bits, I found them all to be Zero. Anyway, when writing them, nothing happend. From the phy data sheet, I learned about the paging technique, which makes the access of registers more complex. I assume, the fault was there.
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I do not change the reserved bits. You know, for enabling 88E1111 Packet Generator you have to write in register 30 page 18
and for accessing reg30 page 18,first you have to write s.th in reg 29. I did all these things, but nothing happens.- Mark as New
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dear fpgaengineerfrankfurt,
I understood how to trigger this "Packet Generator". If you are interested in knowing that, tell me to explain it.- Mark as New
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--- Quote Start --- Thank you dear fpgaengineerfrankfurt , I found the datasheet and I wrote a code which is able to write/read to/from the PHY. I needed to change the MAC speed in register 20.6:4 to 100 Mb/s. --- Quote End --- please help me to how to write/read to/from the PHY via Mdio ?
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