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I investigate the feasibility of implement HDMI, DVI, and Displayport in a design. In this design, the FPGA will have the receiver for HDMI, DVI, and DisplayPort, to receive the signal comes from outside source.
Now I am not sure in following questions: 1. In the PCB, there will be ports of HDMI, DVI, and DisplayPort. Is that possible to implement all these without embedded processor (Nios II or ARM) in FPGA just in normal FPGA? If it is possible, what kind of IP core (soft or hard) needed inside FPGA? 2. If we want to implement HDMI, DVI, and DispalyPort with an embedded processor inside FPGA, it can be softcore Nios II or SOC FPGA with ARM, is anyother IP core needed? Thanks very much.Link Copied
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Anybody can help?
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You will need an external PHY chip to convert the TMDS signals used in DVI and HDMI to a parallel singled-ended format that can be received by your FPGA.
There are some Altera compatible development kits that have these types of chips on them. http://www.bitec-dsp.com/hsmc_dvi.html http://www.microtronix.com/hsmc-daughtercard-solutions/hdmi-1-4-receiver-hsmc-daughter-card http://www.microtronix.com/hsmc-daughtercard-solutions/hdmi-receiver-transmitter-hsmc-daughtercard-1 Also, see this Altera Support Solution question: [h=1]Can I directly connect (DC-couple) TMDS or LVPECL devices with Altera transceivers?[/h]http://www.altera.com/support/kdb/solutions/rd08102012_593.html Looks like this Arria V devkit uses simple level shifters to allow for connecting the TMDS lines to FPGA transceivers: https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=162&no=763&partno=2- Mark as New
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This is very good info, gwall! It seems Bitec is selling eval board / HSMC-<Video> adapters and IP code. All these just come to one price?
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Another source found on HSMC daughter card is available at Terasic, half the price and came with a transmitter or receiver chips as oppose to re-buffer:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=65
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