First time CPLD use questions - internal pull up resistor and clocking with Max 7000S

[Altera_Forum]

I've designed a video game controller using Altera Max 7000s and Quartus 2 using the BDF process.  

 1-Was I suppose to add a clock? I only have inputs and outputs and logic gates needed in the bdf file.  2-Does the EPM7064SLC4410N have an internal clock that is could use? Does this occur by default?  Logic is pretty simple NAND, NOR, OR, and NOT gates. Pins have been assigned. I assign the JTAG pins to the JTAG functions (tdi, tdo, etc).   3-However I want to double check my understanding of the inputs. I set inputs to VCC. I assume this means the pin is high, kind of like internal pull up resistor. The inputs go to external switches that will ground these pins to indicate low. I assume this doesn't short power to ground, right?  Thanks for making such cool products.

[Altera_Forum]

If you only use combinatorial logic, a clock is not strictly required. 

However, in a typical design you have a least one register or a few synchronous functions, so you usually do need a clock. Some CPLD and FPGA have internal clocks available, but they are far from being at precise frequency, since they are generated without a crystal. So, they can be used for very basic clocking, but not for something like driving serial ports or similar functions requiring a stable frequency reference. No matter setting inputs connecting them to VCC or GND: this is what we common do for test purposes. The CPLD internal pull up resistors are not a problem since they usually have a high value, in the tens-of-kohms range. You only must pay attention to not exceed the I/O input voltage range.

[Altera_Forum]

If you only use combinatorial logic, a clock is not strictly required. <-- great 

 However, in a typical design you have a least one register or a few synchronous functions, so you usually do need a clock. ,<-- None, here just a bunch of NAND, NOR, OR, NOT gates  I'm using Block Diagram / Schematic tool, when I add a input and then right click and go to properties. It allows me to set the 'default value' to either VCC or GND. Is this setting used for anything?  I want inputs and outputs to be pulled high internally. How do I do this?   Thanks

[Altera_Forum]

Ok I found setting on Max V CPLD for Weak Pull-up Resistor" after I customize window in pin planner. 

 By weak I assume that means like 4.7Kohms or something, right?   I find no such setting for Max 7000S (EPM7064SLC4410N) <--this is the CPLD I want to use as it supports 5v I/O operation.  Does Max 7000S CPLD support internal pull up resistor, or does it need to use an external pull up resistor?

[Altera_Forum]

Pull up resistors in FPGA and CPLD are not 'real' resistors. They are implemented with a biased MOSFETs, so their characteristic is dependent on the VCCIO voltage. 

Usually the datasheet specifies a maximum sourced current, not the ohmic value which is commonly in the 10k to 100k range; that's why they are referred to as 'weak'. I never used the Max7000 device and I don't have the datasheet here, so I can't tell you if the pull up feature is available.

[Altera_Forum]

I reviewed the datasheet for Max V and it discusses the weak pull resistor, the datasheet for Max 7000S does not mention pull up resistors. This confirms what I saw in Quartus II--> the Max 7000S does not have weak pull up resistor feature. I'll be installing an external pull up resistor on the inputs.