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JET60200
New Contributor I
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Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)).

we use “10AS066H3F34I2LG” device,  and in our hw design, HPS uses shared I/O as following:

* HPS_I2C1_SDA     @ C18    ( SHARED_Q4_1 )
* HPS_I2C1_SCL     @ D17    ( SHARED_Q4_2  )

 

But then building project, it fails to Fitter duo to below error, I don't know what's that means ? 

[

Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (78, 196) to (78, 197), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): hps_i2c1_SCL
Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad hps_i2c1_SCL is constrained to the location PIN_D17 due to: User Location Constraints (PIN_D17) File: /home/hw/a10_ghrd/ghrd_a10_top.v Line: 55
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)
Info (175029): D17
 
Error (175020): The Fitter cannot place logic pin in region (78, 196) to (78, 197), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): hps_i2c1_SDA
Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
Info (175015): The I/O pad hps_i2c1_SDA is constrained to the location PIN_C18 due to: User Location Constraints (PIN_C18) File: /home/hw/a10_ghrd/ghrd_a10_top.v Line:  54
Info (14709): The constrained I/O pad is contained within this pin
Error (175005): Could not find a location with: IO_FUNCTION of HPS_IO (1 location affected)
Info (175029): C18
 
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 9 errors, 2 warnings
Error: Peak virtual memory: 3335 megabytes
Error: Processing ended: Sat Oct 10 17:50:10 2020
Error: Elapsed time: 00:00:25

 

 

 NHOW TO FIX THIS PROBLEM ?  Thanks in advance
 

 

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1 Reply
Eliath_G_Intel
Employee
183 Views

Hi Shenzen,


First of all, thanks for reaching us.


Are you trying to map the pins to the FPGA region? please explain to me a little more of what are you trying to do so i can have a better understanding of what is going on but the first step is to check the pin assignment name that you are not using the same name or assignation for different pins.


Regards,

-Eliath Guzman



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