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Fitter error for fPLL from adjacent bank!

sdfatale
Beginner
484 Views

Hi,

 

  • Currently, I am working on a project where I need fPLLs from an adjacent bank for a transceiver.
  • FPGA part number is 10AS032E3F29I2SG. This is the arria10 SOC family.
  • Transceiver interfaces present are - Bank 1C: 1 PCIe, 4 native phy and Bank 1D: 2 10G baseR, 4 1G 1000baseSX
  • In bank 1D, 2 ATX PLLs are used for tx_serial clcoks of 1G and 10G transceivers
  • In bank 1C, PCIe uses one fPLL_1CB
  • For 4 native phy transceivers, the design needs separate PLL as each transceiver is reconfigurable at different rates. So for this, we are using 1 local fpLL, 1 local ATX PLL (normal mode i.e. without xN), and 2 fPLLs from the above bank (used in xN mode).
  • While trying compilation, the following error is present:
  • Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 CMU_FPLL(s)). Fix the errors described in the sub-messages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Error (175019): Illegal constraint of CMU_FPLL that is part of fPLL Intel Arria 10/Cyclone 10 FPGA IP altera_xcvr_fpll_a10 to the location FPLL_1DB
    Info (14596): Information about the failing component(s):
    Info (175028): The CMU_FPLL name(s): FP_STM.for_stm[2].u_line_serdes_any|U_fpll_xN|xcvr_fpll_a10_0|fpll_inst
    Error (16234): No legal location could be found out of 1 considered location(s). Reasons, why each location could not be used, are summarized below:
    Error (175006): There is no routing connectivity between the CMU_FPLL and destination HSSI_PMA_CGB_MASTER
    Info (175027): Destination: HSSI_PMA_CGB_MASTER FP_STM.for_stm[2].u_line_serdes_any|U_fpll_xN|xcvr_fpll_a10_0|twentynm_hssi_pma_cgb_master_inst
    Error (175022): The CMU_FPLL could not be placed in any location to satisfy its connectivity requirements
    Error (175022): The HSSI_PMA_CGB_MASTER could not be placed in any location to satisfy its connectivity requirements
    Info (175029): 1 location affected
  • Can we do this? or there is some physical limitation to attempting this?
  • I went through the transceiver phy user guide for clock networks. Did not find anything specific to this. I see 2 CGB masters per bank.
  • Your help/interest is appreciated.

 

 

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6 Replies
WZ2
Employee
424 Views

Hi there,

I just receive your question, we will try to help u~


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wchiah
Employee
416 Views

Hi,


You may get this error in the Quartus® Prime software for your based design if you are driving an fPLL and further user logic from the same reference clock pin.


Resolution To avoid this error insert a Clock Control Block (ALTCLKCTRL) Megafunction between the reference clock pin and both the fPLL and the user logic. For further information on using this IP, refer to Clock Control Block (ALTCLKCTRL) Megafunction User Guide (PDF)


Let me know if that is helpful.


Regards,

Wincent_Intel


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sdfatale
Beginner
394 Views

Hi Wchiah,

 

Thank you for showing interest in my query.

 

Unfortunately, after using ALTCLKCTRL too, the same error is present i.e. The Fitter cannot place 1 HSSI_PMA_CGB_MASTER, which is within fPLL Intel Arria 10/Cyclone 10 FPGA IP altera_xcvr_fpll_a10.

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wchiah
Employee
382 Views

Hi,

 

Can I know which version of Quartus you are using ?
Is it possible to sent your .qar file to me ?

Regards,

Wincent_Intel

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wchiah
Employee
334 Views

Hi,

I wish to follow up with you about this IPS case.

Hoping to hear back from you so that we can proceed for next step.

Regards,

Wei Chuan


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wchiah
Employee
329 Views

Hi

 

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.

 

After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

 

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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