Fitter ignoring PLL compensation assignment as invalid

[Altera_Forum]

Hi all,  

Fitter ignoring PLL compensation (source synchronous mode) assignment as invalid. Any ideas as to why this may be happening? I am using Quartus v 10.1

[Altera_Forum]

Can you be a little more specific, and provide some more detail? In source synchronous mode, the PLL compensates the clock so that the clock-data relationship at the pins of the device is maintained at the input register (assuming you don't add any -offset or -phase adjustments to the PLL output clock.)

[Altera_Forum]

I have a LVDS receiver in my design which uses a PLL in source synchronous mode, but when I compile this design, the fitter says that PLL compensation is invalid and ignores it. 

I don't have a clue as to why this is happening. My guess is that I may have to change some fitter settings.  Please help!

[Altera_Forum]

Are you using a Cyclone family device (as opposed to Stratix family)? I assume you are using the ALTLVDS MegaWizard in external PLL mode. Is that correct? What version of Quartus II are you using? You shouldn't see that in 10.1. Anyway, you want the PLL in Normal mode for this situation, although it shouldn't hurt you to be in Source Synchronous mode.

[Altera_Forum]

I am using cyclone iv e device. I am using ALTLVDS Megawizard in internal PLL mode

[Altera_Forum]

Okay. If you are using the ALTLVDS in Internal PLL mode, then you cannot change the feedback mode. It is set to Normal by the tool (at least it should be, and I confirmed this in version 10.1). Perhaps you are using an older version of Quartus II and this was a bug that got fixed, or you are using the External PLL mode and where the user can change the mode.

[Altera_Forum]

In ALTLVDS_RX megafunction, the PLL mode is set to source synchronous mode and the clock is aligned to the centre of the data window at capture point. These settings cannot be changed (I can confirm that this is true in version 10.1). ALTLVDS is not available in Quartus 10.1, you have ALTLVDS_TX or ALTLVDS_RX. Perhaps you are using an older version.

[Altera_Forum]

I'm using 10.1, and when I say ALTLVDS, I mean either ALTLVDS_TX or ALTLVDS_RX. I created a test design with both, and shared the PLL between them, and verified in the Fitter report for the PLL Summary that the mode is set to Normal mode, not Source Synchronous. It makes no sense that it would set it to Source Synchronous, and then tell you that the assignment is invalid. I have no idea why you are seeing that. I guess at this point, I would suggest you delete that instance and try recreating a new one with the MegaWizard. If you are only using the ALTLVDS_RX, or both but not sharing the PLL, then I didn't test that and it could be a bug, but I'd be surprised.