Flex10K and EPC2 configuration Error - Flex10K in continuous Configuration loop.

[Altera_Forum]

Hi All, 

 I am new to Altera. I have a board with Flex10k30 and an EPC2 to configure it. I also have a DSP (ASDP21060) on the board which uses Flex 10k.   I have recently run into an error in configuring my altera. The CNF_DONE pin is not released. The configuration handbook says the nSTATUS pin is pulled low if the Flex10K finds a problem with configuration bit stream (Page 8-8). On checking with the scope I find nSTATUS toggling rendering the configuration mode to loop over continuously. Attached is the nSTATUS when viewed on the scope.  The result is that the Quartus-II programmer is unable to initialize the JTAG chain both the EPC2 and Flex10K are in the configuration mode continuously. All this while CNF_DONE is pulled low.  Please advice how to stop this loop. And how do I verify if the pof file is loaded to EPC correctly. Can the POF file generated be valid and still have errors within it??  Thanks, C Pemmaraju.

[Altera_Forum]

You can stop the configuration loop by pulling nCONFIG low. 

 There is a setting when you create the EPC2 .pof image that indicates whether to retry configuration on error. Turn that off and you will not get the repeating loop. You can program the EPC2 and then verify to confirm its contents are correct.  Which version of Quartus are you using?  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thanks for the reply. I did the same, I pulled the CNF_DONE high to break off from the loop. Is this the only way? Apart from setting the configuration from not running in a loop that is Auto-Restart Configuration on Frame Error option.  On second examination, I found that there are two POF files in my directory which differ in size by a few bytes say file1.pof and file2.pof. Both files are loaded to EPC without any error message. One of the files configures everytime (the bigger size file1.pof). The other puts flex10K and EPC in the loop. Since there is no error on loading, can I safely assume that the file2.pof is complete in its frames? I think there should be a CRC check when the file is loaded and since the CRC is confirming, the file2.pof should be complete and yet may not be a proper bitstream. could this happen?  Is there any way to check such errors? any way to rebuild the RTL from POF file??  The point is I will have to configure the EPC remotely in the future and my card will be completely enclosed and at that time I will not have a chance to pull the CNF_DONE pin.   By the way I am using the Quartus 7.2   Thanks C Pemmaraju

[Altera_Forum]

Where did you get the idea that I suggested to pull CONF_DONE high??? Read the message, I said pull nCONFIG low!! CONF_DONE is released by the FPGA when it completes programming, it you *drive* it high, you will create a driver conflict and damage your FPGAs CONF_DONE output. 

 Look at the .pof files in a binary editor. I vaguely recall that they have the device type in there. Once you figure out the correct .pof image to load, you should not have to deal with the looping, so your remote updates will work fine.  In my FLEX10K systems I use the JamPlayer to remotely update the EPC image. The Jam file checks the device ID, so I have never had any issues with invalid .pof files being loaded.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 You told me to pull down the nCONFIG. But when I checked the nCONFIG was already low. I checked it again now. The situation when in the loop is  1) nSTATUS -- toggling as per the pic I uploaded. 2) continuous DCLK, DATA0 3) nCONFIG --- Low 4) CNF_DONE -- Low  I made a mistake in driving the CNF_DONE high which I will not do again. I am using the nINIT_CONF pin on the EPC2. The configuration handbook says I need not use an external pull up resistor (there is a provision for it on the card) if I am using nINIT_CONF and the internal pull up resistors.   could you tell me why such a situation occurred. There is a mention of JTAG's initialize configuration instruction, but when booting for EPC2, that should not be an issue. Does EPC2 use the nINIT_CONF pin when booting?  Thanks, C Pemmaraju

[Altera_Forum]

nCONFIG should not be low.  

 Here's a schematic of a design containing a FLEX10K and EPC2  http://www.ovro.caltech.edu/~dwh/correlator/pdf/correlator_sch_rev_c1.pdf  p57 has the EPC2, the net names are prefixed with SC_PS for "System controller passive serial". p69 has the system controller FPGA connections.  Note how there is a pull-up on nCONFIG. You will need to do the same.  Cheers. Dave

[Altera_Forum]

Thanks for the answers Dave. 

 I could not reply earlier. I will go through your schematic and update my config.  I will get back if I get into some trouble again....   cheers, C Pemmaraju.

[Altera_Forum]

--- Quote Start ---   I could not reply earlier. I will go through your schematic and update my config.   --- Quote End ---   Ok.    --- Quote Start ---   I will get back if I get into some trouble again....    --- Quote End ---   Sure, I'll respond if I see a response on this thread.  Cheers, Dave