Programmable Devices
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Fmax of design

Altera_Forum
Honored Contributor II
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Hi, 

I designed a processor using VHDL on Quartus II, but I didnt know how to determine its fmax. Where in quartus can report this? Or I should be use ModelSim to check it? Thank you
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Altera_Forum
Honored Contributor II
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Use timequest

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Altera_Forum
Honored Contributor II
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Run timequest. If you have not provided any constraints it will apply a constraint to all signals it determines to be clocks as 1000MHz, then it will give you the FMax in the appropriate temperature model report.

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Altera_Forum
Honored Contributor II
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If you created processor why you don't compute operation per second?? 

but yes you can use TimeQuest and if you will wonder with results you need make analysis of reprot for Analysis and Synthesis phase, that you need to do the same for Fitter phase, then it is all. but have you run Design Space Explore for your project assignments? Hope you do project compilation with real coomands in SDC file.
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Altera_Forum
Honored Contributor II
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I dont understand what is slow 1200mV 85C model? What is 85C? Celsius? 

I set up clock, set input delay, set output delay with 100ns, slow model, fast model are not red. So, fmax in those reports is Fmax of design? And onnly Unconstrained paths is red. What should I do with this red? Thank you.
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Altera_Forum
Honored Contributor II
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How can I compute operation per second? In fact, I had a little experience with quartus as well as timequest timing analyzer. Thanks.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I dont understand what is slow 1200mV 85C model? What is 85C? Celsius? 

I set up clock, set input delay, set output delay with 100ns, slow model, fast model are not red. So, fmax in those reports is Fmax of design? And onnly Unconstrained paths is red. What should I do with this red? Thank you. 

--- Quote End ---  

 

 

That means the timing analysis assumes that the chip is running with a core voltage of 1200mv at 85 degrees celcius. This is what will usually cause the biggest delays in the chip. 

Set input and output delay are meant to compensate for track lengths on your PCB so that signals can be skewed relative to an input clock. They dont affect the FMax. 

 

Timequest will not tell you operations per second. You must know how many clocks there are per operation. So for a given FMax, you can calculate number of ops/s
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