Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18972 Discussions

Fractional PLL fitting Problem Error 11239

cosx
New Contributor I
313 Views

Hi everyone,

I am using HLS Quartus 15.1 standard compiler to design OpenCL BSP components-based systems. I came across an issue in fitting stage and the error is shown below:

Error (11239): Location FRACTIONALPLL_X0_Y1_N0 is already occupied by system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll_0:kernel_pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll.
Info (175015): The PLL output counter system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll_0:kernel_pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter is constrained to the location PLLOUTPUTCOUNTER_X0_Y7_N1 due to: User Location Constraints
Info (14709): The constrained PLL output counter is contained within this fractional PLL

This warning does not make sense as you can see from my attached top.qsf file (in txt) that I have removed the constraints using "#" in line 773 and 774.

Is it because other parts of the constraints in the qsf leads to the failure of PLL placement?

Could anyone please kindly tell me what exactly happened here?

Thank you in advance!

Mingqiang

0 Kudos
2 Replies
BoonBengT_Intel
Moderator
258 Views

Hi @cosx,

Thank you for posting and sharing the finding in Intel community forum, hope this message find you well and apologies for the delayed in response.
We do see from the top files that you using a cyclone v board, just to clarify further on the situation what are the bsp and also board used you have used for the compilation?

Best Wishes
BB

cosx
New Contributor I
251 Views

Hi Mr. BB,

Thank you so much for your reply!

The BSP I used was the acl_kernel_clk, acl_kernel_iface from the opencl platform.

I modified the acl_kernel_clk and add extra PLL modules for multi-clock applications.

The board I used was cyclone V "c5soc".

I have also attached the modified acl_kernel_iface and kernel_clk for your references. (The Quartus version used to compile this system was 15.1.)

Thank you for your help!

Mingqiang

Reply