Hi everyone,
I am using HLS Quartus 15.1 standard compiler to design OpenCL BSP components-based systems. I came across an issue in fitting stage and the error is shown below:
Error (11239): Location FRACTIONALPLL_X0_Y1_N0 is already occupied by system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll_0:kernel_pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll.
Info (175015): The PLL output counter system:the_system|system_acl_iface:acl_iface|system_acl_iface_acl_kernel_clk:acl_kernel_clk|system_acl_iface_acl_kernel_clk_kernel_pll_0:kernel_pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|counter[0].output_counter is constrained to the location PLLOUTPUTCOUNTER_X0_Y7_N1 due to: User Location Constraints
Info (14709): The constrained PLL output counter is contained within this fractional PLL
This warning does not make sense as you can see from my attached top.qsf file (in txt) that I have removed the constraints using "#" in line 773 and 774.
Is it because other parts of the constraints in the qsf leads to the failure of PLL placement?
Could anyone please kindly tell me what exactly happened here?
Thank you in advance!
Mingqiang
