Frame Buffer Avalon Stream problem

[Yarko]

Hello,

I'm using IP cores from Video and Vision Processing Suite Intel® FPGA IP  to process my video stream. I came across a problem and simplified the video pipeline to the following:
Custom TPG -> Frame buffer -> Custom CVO.

There are 3 clock domains: 1) TPG generator 2) AV-ST and AV-MM used by Frame Buffer 3) CVO output to conduit. TPG and CVO use dual clock fifo with two registers to transition between clock domains.

Custom TPG generates a 480*640 (h*w) image and for each row creates next data: 1, 2, 3, ... 639, 640. Then packs them into a video package created by the documentation in the aforementioned VIP Suite. I also send a control packet before each video packet for full compatibility with the Intel IP cores in this set.

The data then goes into the Frame Buffer to eliminate the problem of mismatched framerates (for TPG it is for example 60fps, for CVO it is 59.9 fps).

The problem comes when the data leaves the Frame Buffer and enters my CVO. The picture appears as shown in Figure 1. It turns out that the output lines are missing some pixels and analysis with signaltap showed that this happens from 2-4 line of the very first frame.

Also with the signaltap I was able to find one of the places where data loss occurs. Figure 2 shows how for a pixel with a value of 64 the dout_valid signal is set to 0. Then dout_valid returns but with a pixel value of 65. It is exactly this pixel that is then missing in the row because it will not come into fifo where one of the write conditions is the dout_valid signal must be at 1.

My CVO module has ReadyLatency = 1 for the Avalon Stream protocol. The Frame Buffer has the same value. In the Avalon® Interface Specifications I did not find an explanation for me, maybe I am misunderstanding something. But supposedly even during ReadyLatency cycles after dout_ready signal falls there should be dout_valid signal in 1 if Source wants to send data.

And the last thing is that with the Intel CVO module from VIP Suite everything works... I don't get it

What could be the problem? What am I missing?

Thanks in advance!

Figure 1: resulted image

Figure 2: missing pixel

[Yarko]

There is one more example:

- The value 83 is transmitted correctly and is hold when the valid signal drops.

- But the value 139 is not recognized because the valid signal is 0.

[Yarko · Accepted solution]

The problem turned out to be a missing constraints.

[Wincent_Altera]

Hi Yaros,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.

Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.

However , I am glad that you are able to resolve this problem.

Thanks for sharing with us the way you resolved it as well. We are much appreciate it.

Regards,

Wincent_Intel