Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

Frame Buffer Design

Altera_Forum
Honored Contributor II
‎12-05-2008 08:51 PM
1,089 Views

Hello All,  

I am designing a Custom fram buffer which will have three AV st source ports, which will be able to be enabled and disabled as pleased. But have come to a problem in the method how you manage the write and read ports sucessfully. 

 

any ideas? 

 

What I actualy need is a method to be able to send a video stream to video out and some times if need be record the stream. Hope to hear from you all... thanks 

 

regards nadeem
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.