Quartus 8 & NIOS flash problem...

[Altera_Forum]

This is the problem I am currently experiencing:  

 I'm using a CYC3 which has : - one IS16LV25616 SRAM - 10ns - EPS16 FLASH - 40 MHz clock  I have created a custom memory interface in SOPC wizard (with timings that match the 12ns version of the SRAM) and a NIOS processor with some ONCHIP memory. There is also some peripheral logic into which the NIOS writes. Everything is running on the 40MHz clock. The board was designed according to ALTERA specifications for CYC3.   The problem is: When I download the software through the JTAG to SRAM, the processor runs fine, no problems. If I program the NIOS project (sof + elf) through the Flash Programmer tool inside NIOS IDE the programmer finishes successfully and I power cycle the board. The firmware is loaded ok (LED controlled from firmware), but the processor doesn't run. I do see the access cycles on the EPCS lines for booting the FPGA and processor reading flash.  However if I set the processor to use the ONCHIP memory it boots fine and starts running. And the access to EPCS looks the same.   Does anyone have any ideas what is going on? Or did i stumble upon a bug in the bootloader?  Thanks in advance  Ps: the software bring loaded into ONCHIP or SRAM memory is identical, there are no printf's in the program that would jam the jtag uart and stop the processor.

[Altera_Forum]

have already resolved the problem? I am stumped upon exactly the same problem as you, except that i am using sumsang sram(2MB,32 data width), and the system works at 75MHz. 

 i don't konw if you have set the skew. if not, you should try -3.5ns to -1.17ns (2 cycles of read latency):)    but when i try to set the snew, it still doesn't work when i download the .jic file into the EPCS16I8.:mad:    Does anyone here have ideas about this problem?   Thanks in advance

[Altera_Forum]

--- Quote Start ---  have already resolved the problem? I am stumped upon exactly the same problem as you, except that i am using sumsang sram(2MB,32 data width), and the system works at 75MHz.   i don't konw if you have set the skew. if not, you should try -3.5ns to -1.17ns (2 cycles of read latency):)    but when i try to set the snew, it still doesn't work when i download the .jic file into the EPCS16I8.:mad:    Does anyone here have ideas about this problem?   Thanks in advance  --- Quote End ---    Hi schokolade  Yes we have solved the problem which was hidden in our schematic. While everything on our board was wired correctly the names for our SRAM were mixed up. To clarify: we had the byte enables swapped so when the bootloader started loading SRAM it loaded it incorrectly and hence the processor couldn't start. I did use my own custom design for SRAM with worst case settings (Ts: 1ns, Tr,Twr: 12ns, Th: 2ns) which with the system clock of 40MHz comes to about Tr,Twr 25ns measured.  If there is anything else you need to know just ask :)  Have fun

[Altera_Forum]

Hi milosd 

 I have just solved the problem. The problem is I used the Quartus programmer , not the NIOS flash programmer.    I used to convert the sof file into jic file in Quartus , and then download the jic file into the EPCS through Quartus programmer. That method doesn't work when it comes to Sram, so I always failed.    But this time I download the whole NIOS project(sof+elf) by NIOS flaah programmer, it works.   thanks for answering, good luck !

[Altera_Forum]

Hi milosd 

 I have just solved the problem. The problem is I used the Quartus programmer , not the NIOS flash programmer.    I used to convert the sof file into jic file in Quartus , and then download the jic file into the EPCS through Quartus programmer. That method doesn't work when it comes to Sram, so I always failed.    But this time I download the whole NIOS project(sof+elf) by NIOS flaah programmer, it works.   thanks for answering, good luck !