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Valued Contributor III
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Frame buffer IP

We use 2 frame buffer IPs in our design.  

1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We do not use the read & dout of this Frame buffer . So, these unused interfaces are connected to an empty dummy component (reference to the service request no. 10773449 ) 

2- The second frame buffer: should read the data written by the first Frame buffer in the used SDRAM and gives this data to the DVI out IP (VGA_out_INST). W e do not use the write & din of this Frame buffer. So; these unused interfaces are connected to the same dummy component. 

 

Taking into consideration that, the dummy component interfaces are Avalon. 

 

Kindly advise about the following  

1- Is it applicable to use a Frame buffer to write data in SDRAM and another Frame buffer to read this data from the same SDRAM as described above? 

2- How to make sure that the second frame buffer reads the data from the same addresses used by the first frame buffer for writing in the SDRAM? This question is because the addresses are nit indicated when we instantiated the frame buffer in SOPC builder
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Valued Contributor III
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Re: Frame buffer IP

Is there a reason you are not just using one frame buffer as it is intended to be used? 

 

Or are you trying to manipulate the data in SDRAM as it passes through the system? In this case, it may be easier to just write your own custom IP instead of trying to warp the frame buffer into doing something it was not designed for. The Altera Frame Reader may be usable as is in you application for the output side.
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Valued Contributor III
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Re: Frame buffer IP

Thank you for your reply. 

Usually, one Frame Buffer is used for reading & writing operations. However, I want to separate the reading apart from the writing using 2 different Frame Buffers because there is some processing required after the writing and before the reading (Ethernet TX&RX). This is shown in the attached brief block diagram. 

 

1- Please confirm that: this block diagram is suitable for testing purposes. 

2- If it is suitable, how can we choose the SDRAM address for reading and writing operations done by the Frame Buffer and SGDMA?
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Valued Contributor III
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Re: Frame buffer IP

The attached file is the testing block diagram

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Valued Contributor III
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Re: Frame buffer IP

Kindly see the attached word file

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Valued Contributor III
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Re: Frame buffer IP

I don't have much experience using SGDMA or Ethernet, so I am not going to comment on your overall block diagram. However, there are a couple things that come to mind: 

 

1. Based on the block diagram, it appears that you are trying to send uncompressed 1080p video over ethernet. If you are trying to actually send a full 24 bits/pixel 60 fps, this would be over 3 Gbits/s of data. You won't be able to send that fast using the Altera TSE. 

 

2. Assuming the rest of your block diagram is okay, I still think you should not be using the frame buffer IP at all. For your second frame buffer, you should be able to use the Altera Frame Reader instead. The frame reader lets you specify the SDRAM address to read from. For your first frame buffer you could write a custom component that just writes the video data to whatever address you want.
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Valued Contributor III
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Re: Frame buffer IP

Thank you for your reply

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Valued Contributor III
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Re: Frame buffer IP

In our design using SOPC Builder we want to connect the output port (Avalon stream source) of an IP (clocked video output) to 2 other IPs. But it is not accepted. The clocked video output accepts to be connected to one IP only. 

Kindly advise if there is any block or component or certain IP can be used to solve this problem.
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Valued Contributor III
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Re: Frame buffer IP

I think you'll have to make a custom component for that, with one sink and two sources. Just connect all the signals from the sink to both sources, and for the 'ready' signal, do an 'and' between the signals from the two sources and put the result on the sink. I think it should work. 

Depending on what you connect your component to, you may need to put some FIFOs to handle the cases when your two IPs aren't ready at the same time.
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Valued Contributor III
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Re: Frame buffer IP

You can use an Avalon-ST Splitter Core to achieve that.

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Valued Contributor III
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Re: Frame buffer IP

Thank you for your replies. 

Is it applicable (two replies) when i want to connect the dout of the "clocked video output" to 2 din of two "frame buffers" using SOPC Builder
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Valued Contributor III
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Re: Frame buffer IP

In SOPC Builder, i want to connect the dout of the "clocked video input" to 2 din of two "frame buffers" 

Kindly confirm if it is applicable or not
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Valued Contributor III
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Re: Frame buffer IP

yes, just use the splitter core as told by josyb. It's easier than my solution, I didn't know that this core existed ;)

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Valued Contributor III
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Re: Frame buffer IP

I have a similar situation in which I just want to use a simple SOPC Builder design to frame sync 4:2:2 YCbCr (720p) video in the un-referenced 74.25MHz clk domain... to black burst sync'd 74.25MHz clock domain by using the Clocked Video Input -> Frame Buffer (with DDR2 intf.) -> Clocked Video Output 

 

But even though I uncheck the "video in and out use the same clock" option on the CVI and CVO general parameters options I still get an error message from SOPC builder (Quartus II v10.0) if I try to use a different dout-to-din (or din-to-dout) on the interface between the Frame Buffer and the Clocked Video blocks. 

 

So then what is the purpose of the "video in and out use the same clock" parameter? What is the simplest way to solve my problem of differing frame rate read and/or write using the Video and Image Processing Suite blocks?
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Valued Contributor III
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Re: Frame buffer IP

Thank you for your reply. 

If i use the "Clocked video input" instead of the "Clocked video output", how can we connect the dout of the "clocked video input" to 2 din of two "frame buffers"
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Valued Contributor III
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Re: Frame buffer IP

Is there any component don not need nios to be used for reading data from the SDRAM (instead of the Frame Reader)?

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Valued Contributor III
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Re: Frame buffer IP

Thank you for your co-operation. I use the frame reader in my design with the following settings: 

Bits per pixel per color plane: 8 

Number of color planes in parallel: 3 

Number of color planes in sequence: 1 

Maximum Image width: 1920 

Maximum Image height: 1080 

Master port width: 64 

Read master FIFO depth: 1024 

Read master FIFO burst target: 64 

Use separate clock for the Avalon MM master interface: unchecked  

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not 

1- // Words 

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8)/64 = 259200 

 

2- // Single Cycle Color Patterns 

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame multiplied by the number of single cycles required to represent one pixel
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Valued Contributor III
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Re: Frame buffer IP

I use the frame reader in my design with the following settings: 

Bits per pixel per color plane: 8 

Number of color planes in parallel: 3 

Number of color planes in sequence: 1 

Maximum Image width: 1920 

Maximum Image height: 1080 

Master port width: 64 

Read master FIFO depth: 1024 

Read master FIFO burst target: 64 

Use separate clock for the Avalon MM master interface: unchecked  

Kindly confirm if the following calculations for number the words and the Single Cycle Color Patterns are true or not 

1- // Words 

IOWR(FRAMEREADER_BASE, 5, 259200); // (1920*1080*8*3)/48= 1036800 

 

2- // Single Cycle Color Patterns 

IOWR(FRAMEREADER_BASE, 6, 2073600); // 1920*1080=2073600 number of pixels in the frame multiplied by the number of single cycles required to represent one pixel
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Valued Contributor III
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Re: Frame buffer IP

 

--- Quote Start ---  

We use 2 frame buffer IPs in our design.  

1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We do not use the read & dout of this Frame buffer . So, these unused interfaces are connected to an empty dummy component (reference to the service request no. 10773449 ) 

2- The second frame buffer: should read the data written by the first Frame buffer in the used SDRAM and gives this data to the DVI out IP (VGA_out_INST). W e do not use the write & din of this Frame buffer. So; these unused interfaces are connected to the same dummy component. 

 

Taking into consideration that, the dummy component interfaces are Avalon. 

 

Kindly advise about the following  

1- Is it applicable to use a Frame buffer to write data in SDRAM and another Frame buffer to read this data from the same SDRAM as described above? 

2- How to make sure that the second frame buffer reads the data from the same addresses used by the first frame buffer for writing in the SDRAM? This question is because the addresses are nit indicated when we instantiated the frame buffer in SOPC builder 

--- Quote End ---  

 

 

hi:  

are you still focus on studing the transmitting video signals though ethernet to pc? I have just realizing sdram data transmitted to TSE_MAC by SGDMA to PC, now,I want to save the video data to SDRAM ,now I refer the demo :VIP and want to make it as a start project ,but I find the software is complex... so ,I hope to communicate with you.my email is young_zyj@163.com

 

thanks
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Valued Contributor III
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Re: Frame buffer IP

 

--- Quote Start ---  

You can use an Avalon-ST Splitter Core to achieve that. 

--- Quote End ---  

 

 

hi,  

 

In my SOPC design, I tryed connecting the Deinterlacer "dout" stream source to the Splitter's stream sink, but I get an error message saying: "The sink has a empty signal of 1 bits, but the source does not." So it looks like that since the Splitter core uses the "empty" signal the connecting cores also need to provide the "empty" signal. 

 

Why aren't these cores setup so that they can be connected in SOPC and then ready to go? Must I provide an additional stage before the Splitter sink input and after it's source output inorder to provide the "empty" signal ?
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