Free on-line C to FPGA software

[Altera_Forum]

Hello,  

 I wanted to recommend http://www.c-to-verilog.com (http://www.c-to-verilog.com/) ;    This website has a free on-line compiler which lets users put regular C code and compile it to Verilog. You can use if without registration on the web-page.   There is a screencast video which shows how you can use the websiteIt targets mainly Altera FPGAs and it creates optimized Verilog. It turns the C loops into pipelined operations.    Please write me if you found this useful.    Nadav

[Altera_Forum]

Hi, 

 Before using this tool, may I ask who might be the target engineers for this tool. -HDL engineers are already flooded with a variety of languages, tools, platforms and their bugs and unhelpful documentation. -Both Altera and Xilinx are offering Universities their Matlab platform tools ready with development boards to entise students on the wrong direction ending up with piles of useless code and little understanding of concepts and fundamentals. -I thought you may target DSP software engineers as opposed to fpga DSP and then you will need to bypass HDL altogether and not ask them to edit the verilog. i.e. C-to-fpga directly may suit them to use fpgas without knowing about HDL. -anyway wish you success.

[Altera_Forum]

Hello Kadhiem,  

 A developer does not need to learn a new programming language if this language is "C". Also, when you have a mixed team of programmers and FPGA engineers you can have the programmers submit c code to the engineers and the engineers will prototype the hardware solution within minutes. This allows on-line and interactive work between algorithm people and hardware people.   Nadav

[Altera_Forum]

I had a quick look at the basic ideas of c-to-verilog tool. What I would have preferred to see, a tool that takes care of resource-speed tradeoff. However the tool's module interface is based on free-running default sampling clock. This implies that it can only produce designs sampling on this clock.  

Is there any way you can enter a clock enable signal to control processing for selected samples. This is very helpful for two reasons: -To constrain the module within the system's data flow srchitecture, otherwise the designer will nee extra memory to hold results. - Can be exploited to make the resource-speed tradeoff.

[Altera_Forum]

I am not sure I understand. Can you give me an example ?

[Altera_Forum]

Hi Nadav, 

 If you look at most of altera/xilinx IPs ,I am sure you will find out that they have clk-enable signal(also called output-enable). At register level, this signal ideally should be routed to the enable port of flipflops. Many projects run at one or few clocks but flexible different rates controlled by this clk-enable. In fact many designers use a pull or push architecture where a module decides the processing rate for adjacent module.If say my system needs to get an fft output at a rate decided by my requesting module then I must control the fft processing not just by the clock but also be able to freeze until next active clock otherwise I have to save all fft block then draw up data as required.

[Altera_Forum]

Okay, I understand what you are saying. Yea, it's not supported.