GMII Transmit constraining with respect to in/out clock pins

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GMII Transmit constraining with respect to in/out clock pins

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Hi,

has anyone constrained GMII transmit interface? As you know, GMII has two transmit clocks: one input clock - I'll call it mtx_clk_i - used in MII mode (10/100 Mbps) and one output clock - gtx_clk_o (generated in the FPGA) - used in GMII mode (1000 Mbps). Internally the logic operates on a multiplexed clock between the two mentioned.

I could not find an example of how to constrain output delays with respect to an input and an output clock, with different frequencies.

The input clock: 2.5 Mhz or 25 Mhz

The output clock: 125 MHz

Thanks!

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