Programmable Devices
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SRAM verification error afte change LVDS pins

Altera_Forum
Honored Contributor II
‎11-17-2009 03:41 PM
1,207 Views

I use a SGDMA to stream a Frambuffer from SRAM to Display via LVDS 

 

 

when e put a second LVDS Display to the same pins, i got a SRAM verification error during softwaretransfer from NIOS IDE via jtag. 

 

 

I don't see the relationship between FPGA-LVDS (3R) pins, and the read-write process of SRAM. 

 

 

Do you know, how i kann find the cause of this problem?
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Altera_Forum
Honored Contributor II
‎11-17-2009 04:06 PM
513 Views

It may be a signal integrity problem. If the design was changed, also a timing issue.

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Altera_Forum
Honored Contributor II
‎11-18-2009 08:01 AM
513 Views

ok, thanks. 

 

but, what can i do agains signal integrity problems? 

i have to use this "time Quest" analyser to found/fix the problem?
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