SRAM verification error afte change LVDS pins

[Altera_Forum]

I use a SGDMA to stream a Frambuffer from SRAM to Display via LVDS 

   when e put a second LVDS Display to the same pins, i got a SRAM verification error during softwaretransfer from NIOS IDE via jtag.     I don't see the relationship between FPGA-LVDS (3R) pins, and the read-write process of SRAM.     Do you know, how i kann find the cause of this problem?

[Altera_Forum]

It may be a signal integrity problem. If the design was changed, also a timing issue.

[Altera_Forum]

ok, thanks. 

 but, what can i do agains signal integrity problems? i have to use this "time Quest" analyser to found/fix the problem?