Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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GPIO status during and before programming

Altera_Forum
Honored Contributor II
‎08-24-2010 10:01 AM
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What is the GPIO pin status before programming a EPM7064 cpld(max7000 series) and also during programming? (ie. Whether the pin status is High impedence or pulled low??) 

 

 

In my application one of the GPIO will directly control power module for micro processor. So before programming it, the module should not be enabled. For this purpose, I am posting this question. In Device datasheet it is not mentioned 

 

(Pin status after powering on the unprogrammed cpld??)
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Altera_Forum
Honored Contributor II
‎08-24-2010 05:25 PM
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see page 16 of the Datasheet: 

 

http://www.altera.com/literature/ds/m7000.pdf 

 

 

--- Quote Start ---  

During in-system programming, the I/O pins are tri-stated and pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k¾. 

 

--- Quote End ---  

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