Gated Resets on Cyclone II

[Altera_Forum]

What is Altera's view on the following code: 

 Specifically the reset being gated.   if (nRESET='0' or sOnePPSPulse = '1') then  sOnePPSSet <= '0'; elsif Rising_edge (CLOCK12M) then  if (sReDetOnePPS = '1') then   sOnePPSSet <= '1';   end if; end if;  sOnePPSPulse is a synchronous signal.

[Altera_Forum]

In general, it's frowned upon, but is design dependent. The problem with gated resets is a glitch will reset the structure. The reset probably won't glitch because it's an OR gate. (If it were an AND, and within one clock cycle you switched from one signal to being active to the other, i.e. you never want the condition where both are active and the AND gate outputs a 1, it might glitch through that state. But this is probably all right. Some other points: 

1) If this OR gate resets multiple registers, I would move it outside of the always state, i.e.: assign or_reset = nRESET or sOnePPSPulse; and then use that signal within multiple always blocks. You basically don't want multiple copies of this ORing(synthesis should merge them together, but this is more explicit) 2) The simple fix for this is to register the output of the OR gate first, so you no longer have a gated reset. This delays it going in and out of reset by one clock cycle, but that shouldn't matter, unless... 3) You're using the reset for design logic, not just as a system reset. I would recommend against this. If sOnePPSPulse is just clearing some logic, then make it happen synchronously. If you need it to occur faster(one cycle earlier) then design for that. But I would strongly recommend against using resets for logic. That's not their intended use, and the timing analysis is not always what you want(i.e. you won't get the analysis where the reset flows through the register and feeds downstream logic.)  If you don't understand recovery and removal, I can post something about it.