I am using A max v CPLD. In my Design I am using 3 counter.1st counter is getting a 8 MHz Clk and it is used for Clock division purpose. It is Two bit counter. My next counter is 10 bit counter in which after every 8 clock pulse I want to generate chip select signal low.But here after every 8th clock pulse I am getting glitch. Similarly my third counter is of 9 bit in which I have to generate Chip select but getting glitch at the output. How to remove that glitch please help in that issue. I tried to add constraint to my input clock . By doing this the glitch on my 1st counter is removed. But still getting glitch at output of 2nd and 3rd counter.