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Generated PCIe Gen3x8 example design for stratix 10 s1 board with "Enable DMA" ?

Honored Contributor II

Hello all, 


In order to test and see the "HardIP for PCIe for stratix 10" IP component. I generated the example design from platform designer by configuring PCIe express IP with "Enable DMA option" and having "internal descriptor" enabled. 


when i opened the example design separately , i find pcie IP and a 8kbytes onchip memeory with dual port access. I compiled this, and programmed the fpga and ran the linux driver and application code that was provided while generating example design. but this linux code has simple link test for 100 reads and writes which was passed with no problem. but what i want to test is PCIE dma transfers with descriptor table stuff and all. I know the theory behind it.  


I want a driver and app code that containing below stuff 


1. descriptor table and status table in host 

2. programming point 1. and cpu writes internal registers of descriptor controller at fpga side. 

3. read data mover picking point 2 and loading it into internal fifo via rd_dts_slave port 

4. based on the content of each descriptor. the read data mover should move data from host pc to fpga( read DMA flow). 

5. after the completion of point 4. the descriptor controller must pass MSI interrupt to HOST to update the status table. 




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