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Honored Contributor I

Getting Quartus to implement an altsyncram in MLABs

I have a wide synchronous DP RAM that I would ideally like Quartus to implement in MLABs. The design is parametrised, so I would prefer to specify the memory as AUTO, and let Quartus use M20Ks or MLABs depending on what is best. The instantiation below works fine, but only if I explicitly specify  

altsyncram_component.ram_block_type = "mlab"  


If I instead specify "AUTO" (as below), Quartus will use a block RAM. Its reason for not using MLABs that it gives in fit.rpt is "No - Latch Type Behaviour". Googling this does not seem to produce any useful results.  


Quartus will implement the RAM in MLABs if I remove the read clock enable (clocken1) but I cannot easily do that. As best as I can tell, MLABs do support clock enable signals (but not rden_b). I am using Quartus 16.1 and targeting Stratix V 


How do I tell Quartus I don't care about what resource it uses to implement this particular RAM instance? It's not like AUTO implies all that many guarantees about what exactly the instantiated RAM will do in corner cases such as at startup. Many thanks. 


altsyncram altsyncram_component ( .address_a(address), .data_a(wdata), .wren_a(write_enable), .clock0(clock), .address_b(address), .q_b(spram_rdata), .clocken1(read_enable), .clock1(clock) ); defparam altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.address_reg_b = "CLOCK1", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_b = "NORMAL", altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_output_b = "NORMAL", altsyncram_component.width_a = 640, altsyncram_component.widthad_a = 5, altsyncram_component.numwords_a = 32, altsyncram_component.width_b = 640, altsyncram_component.widthad_b = 5, altsyncram_component.numwords_b = 32, altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.intended_device_family = "Stratix V", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.power_up_uninitialized = "false", altsyncram_component.ram_block_type = "AUTO", altsyncram_component.init_file = "init.mif", altsyncram_component.init_file_layout = "PORT_A", altsyncram_component.read_during_write_mode_port_a = "DONT_CARE", altsyncram_component.read_during_write_mode_port_b = "DONT_CARE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE";
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