[Global Reset for simulation in Altera device] Xilinx has "glbl.v"! Does Altera has??

[Altera_Forum]

Hi Hi, 

Xilinx has the "glbl.v" module connects the Global Set/Reset and Global Tristate signals to the design. The "glbl.v" module must be compiled and loaded along with the design In order to properly reset the design in a Verilog simulation. Toggling the global set/reset emulates the Power-On-Reset of the FPGA. If do not do this, the flip-flops and latches in your simulation enter an unknown state.   Here is the info on "glbl.v" from xilinx website: https://www.xilinx.com/support/answers/1078.html  Does the Altera device need this global reset for running the simulation???:confused::confused: How is the global reset net connected in Altera device? Is it all register or LUT in the device will connected to a global reset???:confused::confused:

[Altera_Forum]

Anyone can help to answer???^^

[Altera_Forum]

You don't need any such module for Altera devices (or Xilinx for that matter). 

 Providing you write you code correctly, Quartus will be able to identify any reset signals and deal with them accordingly. Correctly capturing your code should also mean that your simulation runs as expected without without any 'unknown states'. Make sure your reset code handles every relevant register.  Cheers, Alex