Global clock, virtual pins & incremental compilation

[Altera_Forum]

I'm doing an incremental compilation with a bottom up approach and I've a problem. 

The problem is that on a partition I've the clock management section and so their output go on other partition. In the first partion I've declared theese output as global signal (ofc I've removed the autoassignment of gloabal line, and I put them manually) and I've done the same in the destination partition input. The problem is that quartus give me message (critical warning) like this one:  "Critical Warning: clock port is fed by virtual pin "CLK_X"; timing analysis treats input to the clock port as a ripple clock"  Can I not consider this because then in the top all should be ok because the CLK_X is on a global line or have I to take care of this problem? In the second case what shall I do? I'm sure that should be some constraint I've to give somewhere in order to solve this.  Thx alot.    PS: Please have a look also on my other thread about incremental compilation, I still have a lot of question unresolved about the metodology to be used.. Title: How to start a new design - best way (incremental compilation) Link: http://www.alteraforum.com/forum/showthread.php?t=3380

[Altera_Forum]

Search the Quartus handbook for virtual pins. You'll find a list of cases where you should not use a virtual-pin assignment. Clock inputs are one of those cases.

[Altera_Forum]

Ok, I'll look better, but strange because I've used the TCL scipt generated in the top for the Bottom-Up flow.. It should be a bug if it's the case. 

 Thx for the information Brad

[Altera_Forum]

I last tried those scripts long ago. A clock-related limitation I ran into then still hasn't been enhanced. You might be seeing another limitation rather than a bug (the scripts are provided as a convenience without the intention of them doing everything for you). If you confirm that the scripts created a virtual-pin assignment on an input that the scripts should have known is a clock, then I suggest filing a mySupport service request regardless of whether it is an intended limitation or a bug. 

 The critical warning probably isn't hurting anything if the timing is good when you compile the complete design at the end. I think I'd still do what the Quartus handbook says and not have a virtual-pin setting for any clock input to the lower-level partition being compiled in a separate Quartus project.

[Altera_Forum]

Yes, I'm thinking that this Bottom up flow should be very nice, but it's becoming a pain to learn to use it. 

Moreover I've understood that it's better that I do the assignment by hand instead of using the scripts, but that's not so good imo because you've to be sure to give all the assignement on the sub design if you need to change something in the top in the project phase, whereas I thought that it was a simply matter of regenerate the script and give them to the sub-partition designer.  I hope that all this pain shall give me the result I would like to have (make 3 people work indipendently), preserve some part of the design if some other part will be changed and of course reduce the compilation time that is increasing a lot.  Another thing that I think It'll be a pain is the use of the signal tap, also on the top you've a lot of limitation on its use (or better you've to use it in a different way and I hope the results still be understandable as untill now, because that shall be a real problem if we've to not use Signal Tap as in the past).  Thx Brad for all the suggestions, ofc I'll fill the mysupport service request for this problem.