Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

HDL-embedded SDC commands

Altera_Forum
Honored Contributor II
1,400 Views

Good Day. 

 

I am Trying to remove some warnings comming from I dont know where. 

Regarding the (altera_reserved_tck) 

 

On The Timequest, I see this. 

 

Info: Evaluating HDL-embedded SDC commands 

Info: Entity dcfifo_api1 

Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_ed9:dffpipe16|dffe17a*  

Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_fd9:dffpipe19|dffe20a*  

Info: Entity dcfifo_psk1 

Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_gd9:dffpipe6|dffe7a*  

Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_hd9:dffpipe9|dffe10a*  

Info: Entity dcfifo_s0j1 

Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_vu8:dffpipe17|dffe18a*  

Info: set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_0v8:dffpipe20|dffe21a*  

Info: Entity sld_hub 

Info: set_clock_groups -asynchronous -group {altera_reserved_tck} 

Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}] 

Warning: At least one of the filters had some problems and could not be matched 

Warning: altera_reserved_tck could not be matched with a clock 

Warning: Ignored assignment: set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 

Warning: Argument -group with value altera_reserved_tck could not match any element of the following types: ( clk ) 

 

 

What is wrong on it? or how can I solve it? 

Where are this HDL-embedded SDC commands read from? 

Can I modify them? is it needed? or better do not play with them? 

anyway. What would U recommend to avoid this warnings? 

 

I allready try inserting in the project .sdc file the altera_reserved constraints generated from the Template but still not going away. 

 

Thankyou!
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
628 Views

what version of software are you using?

0 Kudos
Altera_Forum
Honored Contributor II
628 Views

Quartus v 9.1

0 Kudos
Altera_Forum
Honored Contributor II
628 Views

Could it be that the compiler did some optimization and removed/renamed the source/destination of the set_false_path path? So the TimeQuest could not find the path in the post-synthesis netlist and gave out the warning. 

I saw such warnings in my project too and It never causes any problem. Tried to manually find the source/destination node using the exact filter statement and one of the source/destination node was actually missing.
0 Kudos
Reply